Display Timing Controller Low Speed Glitch Suppression
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Solution Overview
Problem
Display devices experience a glitch phenomenon when transitioning from low speed driving mode to normal driving mode due to frame frequency changes, causing luminance differences and polarity repeat issues.
Innovation Solution
A display device with a timing controller that includes first and second control logic units to manage frame frequency changes by expanding the frame length for low speed drive, grouping gate lines, and controlling data voltage polarity to prevent polarity repeat phenomena, thereby suppressing the glitch phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If interlaced low speed driving scheme is used to reduce frame frequency, then power consumption is reduced, but glitch phenomenon and luminance difference occur during mode transition
Solution Approach 1:
The patent applies preliminary action by performing a completeness determination before mode transition. The timing controller checks whether all display lines have been scanned in the current low speed drive frame before allowing transition to normal speed drive. This preliminary verification prevents glitch phenomenon by ensuring data completeness, thus resolving the contradiction between power saving mode and display stability.
2Use of energy by moving object
If frame frequency is reduced for low speed drive, then data transition frequency and power consumption decrease, but polarity repeat phenomenon occurs during frequency change
Solution Approach 1:
The patent implements feedback through the completeness determination mechanism. The timing controller continuously monitors the scanning status of display lines during low speed drive and uses this feedback information to determine whether the frame is complete before allowing mode transition. This feedback loop prevents polarity repeat phenomenon by ensuring all lines are properly scanned, thereby maintaining display quality while preserving power savings.
3Speed
If interlaced driving scheme is used to reduce frame frequency, then frame frequency decreases, but screen flicker occurs during mode conversion
Solution Approach 1:
The patent applies preliminary action by performing completeness determination before mode conversion. The timing controller verifies that all display lines have been scanned in the current low speed drive frame before allowing transition to normal speed drive. This preliminary check ensures luminance consistency and prevents screen flicker by guaranteeing data completeness, thus resolving the contradiction between low frame frequency and luminance stability.
Data Source
AI summary
A display device capable of driving at low speed includes a display panel, on which display lines each including a plurality of pixels are formed, a driver unit for driving the pixels, and a timing controller which controls an operation of the driver unit and includes a first control logic unit and a second control logic unit. When a mode conversion control signal of an on-level is input during a normal drive, in which a length of one frame is set to P, the first control logic unit expands a length of one frame for a low speed drive to (n×P), where n is a positive integer equal to or greater than 2, assigns a length P to each of n sub-frames included in the one frame for the low speed drive, and controls the operation of the driver unit in an interlaced low speed driving scheme.