Display Timing Controller Kickback Voltage Compensation
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Solution Overview
Problem
Display panels experience image quality degradation due to parasitic capacitance between gate and drain electrodes of switching transistors, leading to discrepancies in grayscale voltages applied to liquid crystal and storage capacitors, known as kickback voltages, which become more pronounced as panel size increases and driving speeds accelerate, resulting in non-uniform image quality.
Innovation Solution
A display apparatus is designed with a timing controller, clock generator, data driver, and gate drivers that generate and adjust gate pulse signals and charge share signals to compensate for kickback voltages by optimizing the falling times and charge share periods of gate signals across gate lines, ensuring uniform voltage application across pixels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If display panels are made larger and driving speed is increased, then productivity and resolution are improved, but kickback voltage discrepancies between pixels increase, worsening image quality uniformity
Solution Approach 1:
The patent applies local quality by dividing the display panel into multiple regions (first region and second region) with different charge share periods. The timing controller generates first gate pulse signals with a first charge share period for pixels in the first region, and second gate pulse signals with a second charge share period for pixels in the second region. This allows different regions to have optimized charging characteristics tailored to their specific kickback voltage conditions, thereby maintaining image quality uniformity across the entire large display panel while operating at high driving speeds.
2Measurement precision
If gate signal falling time is reduced to compensate for kickback voltage, then voltage application accuracy is improved, but charge sharing consistency across different pixel positions becomes difficult to maintain
Solution Approach 1:
The patent implements local quality by setting different charge share periods for different regions of the display panel. The timing controller generates gate pulse signals with region-specific charge share periods that are stored in memory and applied according to pixel position. This allows each region to have optimized charging characteristics that account for position-dependent kickback voltage variations, ensuring both voltage application accuracy and charge sharing consistency across all pixels simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces kickback voltages and enhances image quality by ensuring consistent charge sharing across pixels, thereby improving the uniformity and quality of the displayed image.
Implementation Method 1
a data voltage is applied to a liquid crystal capacitor and a storage capacitor for a predetermined time after the switching transistor is turned off
Implementation Method 2
due to a parasitic capacitance existing between the gate and drain electrodes of the switching transistor, distortion may occur in an actual grayscale voltage applied to the liquid crystal capacitor and the storage capacitor
Data Source
AI summary
A display apparatus including: gate lines extending in a first direction; data lines extending in a second direction intersecting the first direction; pixels connected to corresponding ones of the gate lines and data lines; a gate driver to drive the gate lines in response to a gate clock signal; a data driver to drive the data lines; a memory to store charge share signals corresponding to the gate lines; a timing controller controlling the data driver and the gate driver, in response to an externally input control signal and an image signal, and to output a gate pulse signal to the gate lines; and a clock generator configured to generate the gate clock signal in response to the gate pulse signal. The timing controller is configured to output the gate pulse signals according to the charge share signals.