Display Device Timing Controller Level Shifter Interface
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Solution Overview
Problem
The existing interface between a timing controller and a level shifter in display devices fails to effectively transmit information on reverse driving and start clock, leading to issues with scan signal driving and increased complexity, which results in a larger panel driving chip and PCB size due to the need for multiple signal transmission lines and pins.
Innovation Solution
A simplified interface method that reduces the number of signal transmission lines and pins by using an on clock, off clock, and timing start signals to transmit information on reverse driving and start clock, allowing the level shifter to distinguish between forward and reverse driving directions using the off clock during a vertical blank period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simplified interface is used between the timing controller and level shifter, then the number of signal transmission lines and pins is reduced, but the transmission of reverse driving information and start clock information becomes insufficient
Solution Approach 1:
The existing clock signal lines are made multi-functional by using them to carry both clock signals and reverse driving information. The level shifter distinguishes between forward and reverse driving modes by detecting the presence or absence of clock signals during the vertical blank period, thereby eliminating the need for separate control lines while maintaining full information transmission capability.
2Reliability
If multiple signal transmission lines are used to transmit reverse driving information and start clock information, then information transmission is reliable, but the panel driving chip and PCB size increase
Solution Approach 1:
Multiple functions are merged into existing signal lines. The clock signal lines serve dual purposes: transmitting clock signals during active periods and conveying reverse driving information during vertical blank periods. This consolidation reduces the total number of required transmission lines and pins, directly decreasing chip and PCB area while maintaining transmission reliability.
3Ease of manufacture
If the interface is simplified by reducing signal lines, then manufacturing cost decreases, but the ability to support reverse driving functionality is compromised
Solution Approach 1:
The system uses periodic clock signals during the vertical blank period to encode reverse driving information. By transmitting clock signals at specific periodic intervals during this blank period, the level shifter can reliably detect driving mode information without requiring additional dedicated control lines, thus maintaining adaptability while simplifying the interface.
Data Source
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Figure 3A
AI summary
Disclosed is a display device including: a display panel (10); a timing controller (11) generating image data corresponding to an input image, and generating and outputting a first start signal, an on clock (ON_CLK), and an off clock (OFF_CLK); a level shifter (13) generating a second start signal in synchronization with the first start signal, generating gate clocks (GCLKs) that swing to a predetermined voltage and have multiple phases, by using the on clock (ON_CLK) and the off clock (OFF_CLK), and outputting the generated gate clocks (GCLKs); a shift register (14) including multiple stages connected to gate lines (GL) of the display panel (10), respectively, and outputting a scan signal sequentially to the gate lines (GL) by using the second start signal and the gate clocks (GCLKs); and a data driving circuit (12) supplying a data voltage (Vdata) corresponding to the image data to data lines (DL) of the display panel (10) in synchronization with the scan signal.