Display Timing Controller Lock Channel Dual Control
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Solution Overview
Problem
Conventional point-to-point timing controllers in display systems experience high electromagnetic interference (EMI) and difficulty in applying spread spectrum techniques due to high data rates, leading to potential dead lock events in clock and data recovery (CDR) when data rates change.
Innovation Solution
A signal transmitting and receiving system where the lock channel's voltage level can be controlled by both the timing controller and the source driver, allowing for dynamic adjustment of data rates and preventing CDR dead lock events by transitioning between training and data signal transmission states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single data rate is used to transmit frame data, then the transmission is simple, but high electromagnetic interference (EMI) peaks occur
Solution Approach 1:
The patent applies dynamics by making the data rate adjustable rather than fixed. The timing controller dynamically changes the data rate according to different transmission phases: using a first data rate during training signal transmission and a second data rate during data signal transmission. This dynamic adjustment reduces EMI peaks while maintaining transmission efficiency.
2Object-affected harmful factors
If spread spectrum techniques are applied, then EMI is reduced, but the technique is difficult to apply at very high data rates (more than 1 Gb/s)
Solution Approach 1:
The patent changes the data rate parameter to different values depending on the transmission phase. By using a first data rate for training signals and a second data rate for data signals, the system achieves EMI reduction similar to spread spectrum techniques while remaining compatible with high data rate SerDes interfaces (more than 1 Gb/s).
3Adaptability or versatility
If the data rate is changed during the lock channel voltage level corresponding to logic value '1', then data transmission flexibility is improved, but the CDR may happen a dead lock event and fail to sample data correctly
Solution Approach 1:
The patent performs preliminary action by completing the data rate change during the training phase (when lock channel is at logic value '0') before transitioning to data transmission (when lock channel is at logic value '1'). The CDR circuit has sufficient time to lock onto the new data rate during training signal transmission, ensuring stable data sampling when data transmission begins.
4Device complexity
If the lock channel is controlled only by the source driver, then the control is simple, but the timing controller cannot immediately adjust data rates to prevent CDR dead lock
Solution Approach 1:
The patent merges the control functions by allowing both the timing controller and the source driver to control the lock channel voltage level. The timing controller can actively pull the lock channel to logic value '0' to force training phase and data rate changes, while the source driver also controls it based on CDR lock status. This dual control mechanism enables immediate data rate adjustment to prevent CDR dead lock events.
Data Source
AI summary
A signal transmitting and receiving system of a display includes a timing controller and at least one source driver. The timing controller is arranged for transmitting a training signal and a data signal. The source driver is coupled to the timing controller via at least one data channel and a lock channel, and is arranged for receiving the training signal and the data signal via the data channel. The timing controller transmits the training signal or the data signal to the source driver by referring to a voltage level of the lock channel, and the voltage level of the lock channel is allowed to be controlled by both the timing controller and the source driver.