Display Timing Controller Vertical Start Pulse Generation
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Solution Overview
Problem
Conventional electronic display systems using integrated row driver technology consume excessive power due to high-voltage swing clocks, and the use of line buffers to delay active frame data is inefficient, occupying significant die area and consuming power.
Innovation Solution
Providing an indication of a pending active frame start during the vertical blanking period to generate a vertical start pulse, allowing the timing controller to drive multi-clock integrated row driver circuits without delaying the active frame data, thus reducing the need for line buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If line buffers are used to delay active frame data, then the vertical start pulse can be placed subsequent to the active frame start, but the die area and power consumption increase significantly
Solution Approach 1:
The host device provides an indication of the active frame start during the vertical blanking period, before the actual frame data is displayed. This preliminary indication allows the timing controller to generate the vertical start pulse at the correct time without needing to delay the active frame data using line buffers, thereby reducing die area while maintaining timing synchronization
Solution Approach 2:
The patent removes the line buffers from the display circuitry by using the preliminary frame start indication mechanism. The timing controller directly generates the vertical start pulse based on the indication received during the vertical blanking period, eliminating the need for buffering components and reducing overall die area
2Reliability
If line buffers are used to delay active frame data, then the vertical start pulse can be placed subsequent to the active frame start, but power consumption increases excessively
Solution Approach 1:
The host device provides an indication of the active frame start during the vertical blanking period, before the actual frame data is displayed. This preliminary indication allows the timing controller to generate the vertical start pulse at the correct time without needing to delay the active frame data using line buffers, thereby reducing power consumption while maintaining timing synchronization
Solution Approach 2:
The patent removes the line buffers from the display circuitry by using the preliminary frame start indication mechanism. The timing controller directly generates the vertical start pulse based on the indication received during the vertical blanking period, eliminating the buffering components that would consume power and reducing overall power consumption
3Use of energy by stationary object
If multiple clocks are used to reduce clock frequency, then power consumption is reduced, but a vertical start pulse is needed several lines earlier than actual frame start
Solution Approach 1:
The host device provides an indication of the active frame start during the vertical blanking period, giving the timing controller advance notice. This allows the timing controller to generate the vertical start pulse at the correct提前 time required by multi-clock integrated row driver circuits without complicating the timing control logic, as the indication is provided in advance during the blanking period when no active display data is being transmitted
Data Source
AI summary
Devices and methods for providing an indication of an active frame start, while reducing a number of line buffers utilized by conventional systems are provided herein. By way of example, an electronic display panel may include a host device (e.g., a processor) that provides an indication of a pending active frame start. The indication may be provided at a predetermined and fixed time/line interval before the active frame start. Next, a timing controller of the display circuitry may generate a vertical start pulse during vertical blanking based upon the indication and the fixed time/line interval. The vertical start pulse may be used to drive multi-clock integrated row driver circuits.