Display Timing Controller Variable Refresh Rate Luminance Control
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Solution Overview
Problem
Display devices experience issues with pixel degradation and uneven screen quality when operating at low refresh rates, leading to increased screen luminance and visible horizontal lines due to driving transistors operating in saturation, especially at low grayscales.
Innovation Solution
A display device with a timing controller that generates an internal synchronization signal at a frequency equal to the Nth frequency during holding periods, using first and second memories to store and output image data, and a gate driver and data driver to maintain image quality by updating pixel data during these periods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If the display device operates at a low refresh rate, then power consumption is reduced, but the driving transistor operates in saturation area causing increased screen luminance and impaired image quality
Solution Approach 1:
The patent implements variable refresh rate capability that dynamically adjusts the refresh rate based on content requirements. The system can switch between low refresh rates for static content (saving power) and high refresh rates for dynamic content (maintaining image quality), making the refresh rate adaptive rather than fixed.
Solution Approach 2:
The patent changes the operating parameters of the display device by adjusting the refresh rate parameter. When operating at low refresh rates, the system carefully controls the holding period parameters to prevent transistor saturation, while at high refresh rates, it maintains optimal timing parameters to ensure image quality.
2Productivity
If the holding period increases to support lower refresh rates, then power consumption decreases, but the driving transistor operates in saturation area causing uneven screen quality and visible horizontal lines
Solution Approach 1:
The patent applies preliminary compensation actions during the holding period. The timing controller pre-calculates and applies compensation values to counteract the expected luminance increase from transistor saturation, preventing the degradation before it occurs rather than correcting it afterward.
Solution Approach 2:
The patent implements a feedback mechanism where the system monitors for signs of transistor saturation and image quality degradation during the holding period, then adjusts the compensation parameters accordingly. This closed-loop control ensures that screen quality uniformity is maintained even at low refresh rates with extended holding periods.
3Use of energy by stationary object
If the refresh rate is reduced to save power, then energy consumption is reduced, but pixel degradation cannot be sensed during the holding period
Solution Approach 1:
The patent implements periodic sensing actions during the holding period at low refresh rates. Instead of continuous sensing (which would consume more power), the system performs sensing at specific periodic intervals, allowing pixel degradation to be detected while maintaining power savings from the reduced refresh rate operation.
Solution Approach 2:
The patent ensures continuous pixel monitoring capability by maintaining the sensing function active during the holding period, even though the refresh rate is reduced. The sensing operation continues uninterrupted, ensuring that pixel degradation can be detected at any time regardless of the reduced refresh rate.
4Adaptability or versatility
If the display device supports variable refresh rates, then adaptability to different content types is improved, but the timing controller and driver coordination becomes more complex
Solution Approach 1:
The patent designs the timing controller with multi-functional capability to handle both low and high refresh rates using the same basic control architecture. The controller can dynamically switch between different operating modes and adjust parameters universally applicable to various refresh rates, reducing the need for separate dedicated circuits for each mode.
Data Source
AI summary
A display device can include a display panel including sub-pixels and configured to switch between operating at a first frequency and operating at an Nth frequency, the Nth frequency being a maximum operating frequency of the display panel, N being a positive integer, a gate driver configured to output a scan signal to the display panel, and a data driver configured to output a data voltage to the display panel. Also, the display device can further include a timing controller configured to receive an external synchronization signal and image data, generate an internal synchronization signal within the timing controller, the internal synchronization signal having a frequency equal to the Nth frequency, and in response to generating the internal synchronization signal during a holding period, output a gate start pulse to the gate driver and output the image data to the data driver.