Display Timing Controller Staggered Voltage Output
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Solution Overview
Problem
Display apparatuses face challenges in maintaining optimal output timings of data voltages across different display blocks, leading to inconsistencies in display quality due to manufacturing errors and temperature variations, which affect the synchronization of gate and data signals.
Innovation Solution
A display apparatus with a timing controller that analyzes image signal color patterns and temperature information to adjust the output timings of data voltages for specific display blocks, using source driving chips to synchronize data voltage applications, thereby ensuring consistent display quality across all blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data voltages are output simultaneously to all display blocks, then the circuit design is simple, but display quality becomes inconsistent due to manufacturing errors and temperature variations
Solution Approach 1:
The patent applies local quality by differentiating the output timing of data voltages based on specific display blocks. The timing controller adjusts the output timing of data voltages for predetermined display blocks differently from other blocks, allowing localized compensation for manufacturing errors and temperature variations in specific areas of the display panel.
Solution Approach 2:
The patent implements dynamics by making the output timing of data voltages adjustable and variable. The timing controller dynamically changes the output timing based on color patterns of image signals and temperature information, transitioning from fixed simultaneous output to flexible staggered timing to optimize display quality under different conditions.
2Manufacturing precision
If data voltage output timings are adjusted for each display block, then display quality consistency improves, but the control system becomes more complex
Solution Approach 1:
The patent applies preliminary action by pre-defining multiple predetermined display blocks and their corresponding staggered output timings before operation. The timing controller is configured in advance to output data voltages to different display blocks at different timings, eliminating the need for real-time complex calculations during operation.
Solution Approach 2:
The patent implements parameter changes by adjusting the output timing parameter of data voltages based on observable conditions such as color patterns of image signals and temperature information. The timing controller changes the timing parameter dynamically according to these external parameters while maintaining a relatively simple control architecture.
3Speed
If data voltages are output without timing adjustment, then the response speed is fast, but temperature-induced delays cause display defects
Solution Approach 1:
The patent applies preliminary anti-action by proactively compensating for temperature-induced delays through staggered output timing before the actual display issues manifest. The timing controller anticipates the delays caused by temperature variations and manufacturing errors and adjusts the output timing in advance to counteract these harmful effects.
Solution Approach 2:
The patent implements dynamics by making the output timing adaptable to temperature conditions. The timing controller adjusts the timing of data voltage output dynamically based on temperature information, maintaining optimal performance across varying temperature environments while preserving fast response characteristics.
Data Source
AI summary
A display apparatus includes a display panel including display blocks, where each of the display blocks includes a plurality of pixels, a gate driver which outputs gate signals to the pixels, a data driver which receives image data and outputs data voltages corresponding to the image data to the pixels, and a timing controller which converts an image signal input thereto, outputs the converted image signal to the data driver as the image data, and controls a driving timing of the gate driver and the data driver. The timing controller controls output timings of at least data voltages output to pixels of a predetermined display block among the data voltages provided to the pixels of the display blocks, depending on a color pattern of the image signal corresponding to the pixels of the predetermined display block.