Display Timing Control Using Dual Clock Segmentation
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Solution Overview
Problem
Existing display apparatuses face challenges in generating highly accurate timing signals, especially scanning clock signals, at high frequencies, which leads to increased power consumption and cost due to the need for expensive logic ICs, and results in display unevenness and high manufacturing costs.
Innovation Solution
A display apparatus with a timing control unit that acquires delay amounts and generates scanning clock signals by combining a low-frequency first clock signal with a high-frequency second clock signal, allowing for stable and cost-effective generation of scanning clock signals in a short time unit, using an inexpensive logic IC like CPLD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a high-frequency clock signal is used to generate timing signals in a short time unit, then the timing precision is improved, but the power consumption increases and the counter circuit operation becomes unstable
Solution Approach 1:
The patent divides the timing generation into two stages: a first counter circuit generates timing signals at a low frequency (first clock signal) for stable operation, while a second counter circuit generates timing signals at a high frequency (second clock signal) only when short time unit adjustment is needed. This segmentation allows the system to achieve high timing precision on demand without continuously consuming high power.
Solution Approach 2:
The patent dynamically switches between two clock signals (first and second clock signals) based on the required timing precision. The system can adaptively select which counter circuit to use, transitioning from low-frequency stable operation to high-frequency precise adjustment only when necessary, thereby optimizing the balance between power consumption and timing precision.
2Measurement precision
If a high-frequency clock signal is used to generate highly accurate timing signals, then the timing accuracy is improved, but expensive logic ICs such as FPGA are required, increasing manufacturing cost
Solution Approach 1:
The patent segments the timing generation function into two parts: a first counter circuit operating at low frequency that can be implemented with inexpensive logic ICs, and a second counter circuit operating at high frequency that is only activated when high precision is needed. This allows the majority of the system to use cost-effective components while still achieving high timing accuracy when required.
Solution Approach 2:
The patent changes the operating parameters (clock frequency) of the counter circuits based on the required timing accuracy. By switching between a first clock signal with a first frequency and a second clock signal with a second frequency, the system can achieve high timing accuracy only when necessary, allowing the use of less expensive logic ICs for the majority of operations.
3Ease of manufacture
If a low-frequency operating clock signal is used to reduce power consumption and cost, then power consumption and manufacturing cost are reduced, but timing signals adjusted in a short time unit cannot be generated
Solution Approach 1:
The patent implements a dynamic timing generation system that can switch between two operating modes: using a first counter circuit with a low-frequency clock signal for normal operation, and using a second counter circuit with a high-frequency clock signal when short time unit adjustment is required. This dynamic capability allows the system to maintain cost-effectiveness while preserving the ability to generate highly precise timing signals when needed.
Data Source
AI summary
A display apparatus is disclosed. The display apparatus according to one Embodiment comprises: a plurality of pixels arranged in a matrix; a plurality of scanning lines; a plurality of data lines; a scanning line drive unit to generate a scanning signal for selecting a group of pixels arranged in the row direction based on a scanning clock signal and successively output the generated scanning signal to the plurality of scanning lines; a data line drive unit to output, to a plurality of data lines, data signals for supplying voltages to the group of pixels arranged in the row direction; and a timing control unit to control the drive timing of the scanning line drive unit and the data line drive unit based on a first clock signal, and to generate the scanning clock signal based on the first clock signal.