Display Timing Controller Jitter Reduction via Frequency Multiplication

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Solution Overview

Problem

Image defects occur due to jitter accumulation in signals generated based on the horizontal synchronization signal in display apparatuses, leading to noise and image quality issues.

Innovation Solution

A display apparatus that adjusts timing on an oscillator clock period basis based on an internal synchronization signal, and increases the frequency of an external synchronization signal by a predetermined multiple to generate a horizontal synchronization signal, thereby reducing jitter in scan pulses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the external synchronization signal frequency is increased by a predetermined multiple to generate the horizontal synchronization signal, then the jitter in scan pulses is reduced and image quality is improved, but the device complexity increases due to additional frequency multiplication circuitry

Engineering Contradiction:
Improvetiming precisionVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The timing controller integrates multiple functions including external synchronization signal reception, frequency multiplication by a predetermined multiple, internal synchronization signal generation, and scan pulse generation into a single device. This merging approach achieves precise timing control through frequency multiplication while avoiding the need for separate dedicated circuits for each function, thereby reducing overall device complexity despite the enhanced timing precision requirements.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If timing is adjusted on an oscillator clock period basis based on internal synchronization signal, then jitter accumulation is minimized and image defects are reduced, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvesignal stabilityVSAvoidtiming adjustment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The timing adjustment is performed on an oscillator clock period basis, utilizing periodic timing intervals derived from the oscillation clock. By synchronizing timing adjustments to these periodic clock cycles, the system minimizes jitter accumulation in scan pulses while maintaining achievable manufacturing precision through standardized periodic reference points rather than requiring arbitrary high-precision timing adjustments.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250157418A1Display apparatus
Publication Date: 2025.05.15 LG DISPLAY CO LTD
  • US20250157418A1 patent drawing
  • US20250157418A1 patent drawing
  • US20250157418A1 patent drawing

AI summary

A display apparatus may include a display panel including a plurality of pixels, and a controller configured to control an operation of the display panel. The controller may be configured to generate an internal synchronization signal including one or more of an internal horizontal synchronization signal and an internal vertical synchronization signal, based on an external synchronization signal input thereto, the external synchronization signal having a frequency that increases by a multiple, and generate a scan pulse signal to scan the display panel, based on one or more of the generated internal horizontal synchronization signal and the generated internal vertical synchronization signal.