Display Timing Synchronization for Low-Power Video Playback
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Solution Overview
Problem
Conventional power management techniques during video playback in processing systems result in long-term drift and synchronization issues, particularly affecting audio/video synchronization, and require additional hardware for maintaining synchronization, which increases power consumption.
Innovation Solution
A display processing device implements power management operations during video playback by transitioning multiple components into a low-power state during each frame, using a synchronized counter driven by an audio clock to maintain continuous frame synchronization with minimal jitter and no long-term drift, and resynchronizes using a snapshot of the counter value as a reference point.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If components are placed into a low-power state during non-active portions of video playback, then power consumption is reduced, but audio/video synchronization drift occurs
Solution Approach 1:
The system performs preliminary actions by capturing a snapshot of the counter value before entering low-power state and calculating advance adjustment values. This allows the system to pre-compute the necessary phase adjustments so that when components wake up from low-power state, they can immediately resume synchronized operation without drift accumulation.
Solution Approach 2:
The system implements feedback by continuously monitoring the counter value, comparing it against expected values, and calculating adjustment values based on the detected drift. The display controller uses this feedback to adjust the timing of frame rendering and output, ensuring that synchronization is maintained even after components transition through low-power states.
2Reliability
If additional hardware is added to maintain synchronization during power management, then synchronization reliability is improved, but power consumption increases
Solution Approach 1:
The counter serves multiple functions: it tracks video frame timing, generates synchronization signals, and provides reference values for calculating power management adjustments. The display controller also performs multiple functions including rendering frames, managing power states, and adjusting timing based on counter feedback. This multi-functionality eliminates the need for separate dedicated hardware for each function.
Solution Approach 2:
The patent merges the synchronization maintenance function into the existing display controller and counter infrastructure. Instead of adding separate hardware dedicated solely to synchronization, the system combines power management control, timing reference, and synchronization adjustment all within the display controller using the existing counter, thereby avoiding additional power-consuming hardware.
3Reliability
If components remain in active state during video playback, then synchronization is maintained, but power consumption increases
Solution Approach 1:
The system implements periodic action by transitioning components to low-power state during vertical blanking intervals and other non-active portions of video playback. The counter continues to run periodically, and the system periodically adjusts timing based on captured snapshot values, allowing components to sleep while maintaining synchronization capability.
Solution Approach 2:
The system dynamically adjusts the operational state of components based on the video playback timeline. Components transition between active and low-power states dynamically according to frame boundaries and timing requirements. The display controller dynamically calculates and applies timing adjustments to ensure smooth transitions without synchronization disruption.
Data Source
AI summary
A display processing device includes a display device interface and a processing unit. The processing is configured to transition at least a first component of the display processing system into a low-power state in response to an active region of a first video frame of a plurality of video frames having completed. A second component of the display processing device is configured to maintain a temporal count value corresponding to a current frame line of the plurality of video frames, and further to generate a first signal in response to the temporal count value corresponding to a first trigger value. The first signal causes the at least first component to transition out of the low-power state.