Display Device Timing Control for Luminance Uniformity

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Solution Overview

Problem

In liquid crystal display devices, the divisional drive technology leads to luminance issues at the center of the screen during solid displays due to timing mismatches between gate scanning and video signal output, especially when scanning from the edge towards the center, resulting in decreased image quality.

Innovation Solution

A display device with subdivided regions and advanced timing control, including adjustable delay amounts and pre-charge data generation, ensures synchronized video signal output during gate scanning, with larger delay amounts and pre-charge data for the centermost pixels to maintain luminance, particularly during flyback periods and solid displays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of moving object

If divisional drive is employed with gate scanning from edge toward center, then write time per pixel is increased, but luminance at center of screen decreases due to timing mismatch between gate scanning and video signal output

Engineering Contradiction:
Improvewrite time per pixelVSAvoidluminance at center of screen
Core Design Contradiction:
Duration of action of moving objectVSIllumination intensity

Solution Approach 1:

The patent applies preliminary action by outputting the video signal for the centermost line (last line) in advance during the flyback period before the gate scanning reaches that line. This allows the liquid crystal molecules to begin changing orientation before the actual display timing, ensuring sufficient response time and maintaining proper luminance at the center of the screen when using divisional drive with edge-to-center scanning.

Inventive Principle:
Principle #10Preliminary action

2Illumination intensity

If pre-charge data is used with center-optimized setting value, then luminance uniformity is improved for non-divided driving, but pre-charge effects become more noticeable at first line during divisional drive from center toward edge

Engineering Contradiction:
Improveluminance uniformityVSAvoidimage quality at first line
Core Design Contradiction:
Illumination intensityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by differentiating the pre-charge data settings based on the scanning direction and region. When scanning from center toward edge in divisional drive, the first line (at the center) receives different pre-charge treatment compared to other lines. The control unit adjusts pre-charge parameters specifically for the first line to minimize visible pre-charge effects while maintaining luminance uniformity across the display.

Inventive Principle:
Principle #3Local quality

3Reliability

If video signal timing is delayed for distant video signal lines, then timing synchronization is improved, but overall signal transmission time increases

Engineering Contradiction:
Improvetiming synchronizationVSAvoidsignal transmission time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies segmentation by dividing the video signal lines into multiple groups, with each group having its own delay amount stored in the register unit. This allows precise, granular timing adjustment for different segments of the display, achieving synchronization without unnecessarily delaying all signals. The delay is applied only to specific line groups that require it, minimizing overall transmission time while ensuring proper timing alignment.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9489901B2Display device
Publication Date: 2016.11.08 PANASONIC INTELLECTUAL PROPERTY CORP OF AMERICA
  • US9489901B2 patent drawing
  • US9489901B2 patent drawing
  • US9489901B2 patent drawing

AI summary

A display device includes a divided display region that includes pixels and gate drivers each configured to scan gate lines included in the divided display region. The display device also includes source drivers each configured to output, for each of groups of data lines, a video signal based on a grayscale signal in order from a corresponding gate driver side based on each delay amount set in advance and a register unit configured to store the each delay amount. The register unit stores the each delay amount so that, when at least one gate driver scans in a first order from an edge of the divided display region toward a center, the video signal corresponding to the pixels positioned on a centermost side of the display region is output to the pixels, in a period including a part of a vertical flyback period of after one frame period has finished.