Display Timing Synchronization via Transport Agnostic Protocol

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Solution Overview

Problem

Existing display interface solutions, such as HDMI and DP, suffer from tightly coupled timings between content sources and display panels, leading to reduced performance and increased power consumption, and lack effective mechanisms for inter-frame timing management and low latency synchronization, especially in scenarios like wall-of-displays and emerging display technologies.

Innovation Solution

The Transport Agnostic Display (TAD) protocol decouples content refresh rates from panel refresh rates, using presentation timestamps and synchronization timestamps to enable flexible timing synchronization over various transports, allowing for independent panel timings and minimizing latency through region-based panel management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If tightly coupled timings are used between content source and display panel, then synchronization is simplified, but performance is reduced and power consumption increases

Engineering Contradiction:
ImprovesynchronizationVSAvoidperformance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the timing control into two independent parts: content source timing and display panel timing. The content source operates at its own refresh rate while the display panel operates at its own refresh rate, with separate timing management for each component rather than a unified coupled timing system.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary mechanism (frame buffer and timing synchronization protocol) that mediates between the content source and display panel. This intermediary allows asynchronous operation by buffering content frames and managing the timing conversion between different refresh rates, enabling independent timing control while maintaining visual synchronization.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Device complexity

If tightly coupled timings are used between content source and display panel, then timing management is simplified, but power consumption increases

Engineering Contradiction:
Improvetiming managementVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by stationary object

Solution Approach 1:

The timing management is segmented into independent content source timing and display panel timing systems. Each operates autonomously at its optimized refresh rate, with the frame buffer serving as an independent timing management layer that handles the coordination without requiring tight coupling between source and panel.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The frame buffer performs preliminary action by pre-buffering content frames before they are displayed. This allows the content source to operate independently and write frames to the buffer at its own timing, while the display panel reads from the buffer at its own timing, eliminating the need for synchronized operation and reducing power consumption.

Inventive Principle:
Principle #10Preliminary action

3Adaptability or versatility

If traditional display interfaces are used, then compatibility is maintained, but inter-frame timing management and low latency synchronization are lacking

Engineering Contradiction:
ImprovecompatibilityVSAvoidlatency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements a universal timing synchronization mechanism that works across multiple display interfaces and transport protocols. The frame buffer and timing management system are designed to be transport-agnostic, supporting various interface standards while providing consistent low-latency synchronization and inter-frame timing management functionality.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system performs preliminary timing preparation by pre-synchronizing frame timestamps and pre-buffering content frames with their associated timing information. This preliminary action enables low-latency display by having frames ready for immediate presentation when the display panel is ready, reducing synchronization delays without sacrificing compatibility.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11653073B2Timing synchronization between a content source and a display panel
Publication Date: 2023.05.16 INTEL CORP
  • US11653073B2 patent drawing
  • US11653073B2 patent drawing
  • US11653073B2 patent drawing

AI summary

Technology for a display device is described. The display device can include at least one display screen operable to show at least one display panel. The display device can include a controller. The controller can receive a content frame from a content source over a transport topology. The controller can receive a presentation timestamp (PTS) associated with the content frame, where the PTS indicates an earliest time at which the content frame is to be displayed at the display device. The controller can provide the content frame for display on the display panel at a subsequent panel refresh opportunity in accordance with the PTS.