Display Timing Synchronization with Clock-Based Controller Shutdown

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Solution Overview

Problem

Existing OLED display devices face high power consumption and production costs, particularly in low power applications, which affect battery durability and operational efficiency.

Innovation Solution

A synchronization method and electronic device design that allows the display controller to be fully powered off during low power modes while maintaining synchronization with the display driver integrated circuit using an additional clock signal, reducing power consumption by selectively outputting either a synchronization or clock signal through a multiplexer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the display controller continuously generates synchronization signals to maintain synchronization with the display driver integrated circuit, then synchronization reliability is improved, but power consumption increases

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoiddisplay controller power consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system uses periodic clock signals instead of continuous synchronization signals. The display controller can enter a low-power state between clock cycles, generating power consumption nearly to zero while maintaining synchronization capability through the periodic clock signal from the display driver integrated circuit.

Inventive Principle:
Principle #19Periodic action

2Use of energy by moving object

If the display controller is fully powered off to reduce power consumption, then power consumption is reduced nearly to zero, but synchronization with the display driver integrated circuit is lost

Engineering Contradiction:
Improvedisplay controller power consumptionVSAvoidsynchronization
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The clock signal acts as an intermediary that maintains synchronization between the display controller and display driver integrated circuit even when the display controller is powered off. The display driver integrated circuit continues to generate and send clock signals, serving as a mediator that preserves the synchronization relationship without requiring active power consumption from the display controller.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Illumination intensity

If LTPS display panel technology is used to achieve high resolution and high brightness, then display quality is improved, but power consumption and production cost increase

Engineering Contradiction:
Improvedisplay brightnessVSAvoidpower consumption
Core Design Contradiction:
Illumination intensityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the display controller's operational state based on display content requirements. For static content, the controller enters a low-power state with nearly zero power consumption. For dynamic content requiring frequent updates, the controller activates to generate synchronization signals, thus adapting power consumption to actual display needs while maintaining high brightness capability when required.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250299628A1Low power display timing synchronization between soc and display driver integrated circuit
Publication Date: 2025.09.25 MEDIATEK INC
  • US20250299628A1 patent drawing
  • US20250299628A1 patent drawing
  • US20250299628A1 patent drawing

AI summary

An electronic device includes a display controller, a clock generator, a multiplexer, and a processor. The display controller includes an interface, where the display controller provides a synchronization signal through the interface. The clock generator generates a clock signal. The multiplexer outputs either the synchronization signal or the clock signal as an output signal. When the processor needs to reduce power consumption of the display controller, the processor controls the multiplexer to output the clock signal as the output signal.