Display Panel Transistor Insulating Layer for Short-Channel Leakage
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Solution Overview
Problem
High-resolution display panels face design limitations and reliability issues due to the Short Channel Effect (SCE) and Hot Carrier Effect (HCE) in transistors, leading to increased leakage current and reduced insulation properties.
Innovation Solution
The display panel design includes a transistor structure with a specific insulating layer configuration, where the thickness of the insulating layer is gradually increased towards the drain region, forming steps to reduce the electric field and prevent phenomena like Drain Induced Barrier Lowering (DIBL) and Gate Induced Drain Leakage (GIDL), thereby enhancing the reliability of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel length of the transistor is reduced to achieve high resolution, then the pixel density and display quality are improved, but the Short Channel Effect and Hot Carrier Effect increase causing higher leakage current and reduced reliability
Solution Approach 1:
The insulating layer is designed with non-uniform thickness, having a first thickness in the first region and a second thickness greater than the first thickness in the second region. This local variation in insulating layer thickness creates different electrical characteristics in different regions of the transistor, allowing the thicker second region to mitigate SCE and HCE effects while maintaining the overall small transistor size required for high resolution displays
Solution Approach 2:
Instead of only reducing channel length in the horizontal dimension to achieve smaller transistors, the invention introduces a vertical dimension solution by varying the insulating layer thickness. The insulating layer has different thicknesses at different positions, adding a vertical control mechanism to compensate for the negative effects of reduced channel length
2Device complexity
If the channel length is reduced for high resolution, then the transistor size is decreased, but the leakage current increases due to Short Channel Effect and Drain Induced Barrier Lowering
Solution Approach 1:
The insulating layer thickness is locally optimized with a thicker second region positioned to specifically address the drain region where DIBL and leakage current issues occur most severely, while the first region maintains a thinner profile to minimize overall device size and capacitance
Solution Approach 2:
The insulating layer acts as an intermediary structure between the gate electrode and the channel region. By strategically varying its thickness, it mediates the electric field distribution to reduce DIBL effect and suppress leakage current without requiring larger transistor dimensions
3Manufacturing precision
If the channel length is reduced to increase pixel density, then the display resolution is improved, but the Hot Carrier Effect and insulation properties deteriorate
Solution Approach 1:
The insulating layer is designed with spatially varying thickness to locally address Hot Carrier Effect in critical regions. The thicker second region in the second position provides enhanced insulation where HCE is most problematic, while maintaining overall compact transistor structure for high pixel density
Solution Approach 2:
The invention changes the physical parameter of insulating layer thickness from a uniform value to a spatially varying value. This parameter modification allows targeted suppression of Hot Carrier Effect in regions where it most impacts transistor reliability, while preserving the small transistor size needed for high resolution displays
Data Source
AI summary
A display panel of the inventive concept includes a light emitting element, a pixel circuit including a first transistor and electrically connected to the light emitting element, and a first insulating layer. The first transistor includes a first semiconductor pattern arranged under the first insulating layer and including a first source region, a first drain region, and a first channel region arranged between the first source region and the first drain region, and a first gate arranged on the first insulating layer and overlapping the first channel region. The first insulating layer includes a first region overlapping a normal region of the first gate and the first source region, and a second region which overlaps a protruding region of the first gate, has a thickness greater than that of the first region, and is disposed close to the first drain region than the first region.