Display Transistor Capacitance Optimization via Local Quality
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Solution Overview
Problem
Existing display devices face challenges in optimizing the operating characteristics of transistors in both the display area and the driving circuit area, leading to inefficiencies in capacitance management and potential luminance variations in pixels.
Innovation Solution
A display device is designed with a substrate having distinct areas for display and driving circuits, featuring transistors with optimized structures. The first transistor in the display area has a double gate structure with a first lower electrode under the semiconductor pattern layer, while the second transistor in the driving circuit area also has a double gate structure but with a second lower electrode disposed under the semiconductor pattern layer. This configuration allows for differentiated capacitance formation between the semiconductor pattern layers and the lower electrodes, optimizing the operating characteristics of each transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a unified transistor structure is used in both display area and driving circuit area, then manufacturing process is simplified, but operating characteristics cannot be optimized for different functional requirements
Solution Approach 1:
The patent applies local quality by configuring transistors in the display area with a first structure (gate electrode above semiconductor pattern layer) while transistors in the driving circuit area use a second structure (gate electrode below semiconductor pattern layer). This allows each region to have transistor structures optimized for its specific functional requirements, resolving the contradiction between manufacturing simplicity and operating characteristic optimization.
2Stability of the object's composition
If capacitance is increased in display area transistors, then luminance stability improves, but pixel response speed decreases
Solution Approach 1:
The patent implements local quality by using different transistor structures in different areas: display area transistors use a configuration that minimizes parasitic capacitance for fast response, while driving circuit area transistors use a configuration that provides sufficient capacitance for stable operation. This resolves the contradiction between luminance stability and response speed by applying area-specific optimizations.
3Reliability
If different transistor structures are used in display area and driving circuit area, then operating characteristics are optimized, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the display device into two functional areas (display area and driving circuit area) with distinct transistor structures. This segmentation allows independent optimization of each area's transistor characteristics while maintaining overall device functionality, resolving the contradiction between operating characteristic optimization and manufacturing complexity.
4Speed
If parasitic capacitance is minimized in display area, then pixel switching speed increases, but driving capability decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality through area-specific transistor designs: display area transistors are configured to minimize parasitic capacitance for fast switching, while driving circuit area transistors are configured with sufficient capacitance for strong driving capability. Each area's transistor structure is locally optimized for its specific functional requirements.
Data Source
AI summary
A display device includes a substrate including a display area and a driving circuit area, a first insulating layer, a second insulating layer on the first insulating layer, a first transistor in the display area, and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer, and a second transistor in the driving circuit area, and including a second semiconductor pattern layer formed as the semiconductor layer, a second gate electrode on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, wherein the first lower electrode is between the substrate and the first insulating layer, and the second lower electrode is between the first insulating layer and the second insulating layer.