Display Substrate Transistor Layout for Fast Charging and Low Leakage
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Solution Overview
Problem
The increase in pixel density and refresh rate of display panels is limited by parasitic capacitance in data lines, and high current densities lead to transistor failures, such as negative drift or data line-gate line shorts, causing driving circuit failures.
Innovation Solution
A display substrate design featuring a transistor structure with a dual-gate configuration during discharge and a single-gate configuration during charge, utilizing a specific electrode configuration to reduce leakage current and manage high current densities, including a first source-drain electrode, a second source-drain electrode with sub-electrodes, and a gate electrode, all positioned to avoid contact with the active layer pattern, with via connections through insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional single-gate transistor structure is used, then the manufacturing process is simple, but the leakage current is high and charging speed is limited
Solution Approach 1:
The patent implements a dynamic gate structure where the second gate electrode can be selectively connected to power supply voltages (Vdd or Vss) through control switches. This dynamic configuration allows the transistor to switch between single-gate and dual-gate modes operationally, enabling fast charging when needed while maintaining manufacturing simplicity. The dynamic connection approach resolves the contradiction by providing high-speed performance only when required, rather than permanently complicating the structure.
Solution Approach 2:
The gate electrode is segmented into a first gate electrode and a second gate electrode, which are positioned at different locations relative to the active layer. The second gate electrode is disposed over the data line and can be independently controlled. This segmentation allows the transistor to function as a dual-gate device for enhanced performance while maintaining a structured, manufacturable design. The segmented gates enable independent control of different transistor regions, achieving fast charging without excessive structural complexity.
2Speed
If the pixel circuit components are enlarged to reduce parasitic capacitance, then the charging speed improves, but the pixel density decreases
Solution Approach 1:
The patent changes the electrical parameters of the transistor by introducing a second gate electrode that can be independently biased. By controlling the voltage applied to the second gate, the transistor's effective channel characteristics are modified, enabling faster charging speeds without increasing the physical dimensions of the pixel circuit. This parameter control approach allows optimization of charging performance while maintaining small pixel area for high density.
Solution Approach 2:
The second gate electrode acts as an intermediary element that mediates between the data line and the active layer. It provides an additional control point that influences charge transport without requiring larger transistor dimensions. The second gate serves as a mediator that enhances charging speed through electrical control rather than physical scaling, thus resolving the contradiction between speed and area.
3Speed
If the transistor current is increased to improve charging speed, then the charging performance improves, but the leakage current increases
Solution Approach 1:
The patent implements a feedback mechanism where the second gate electrode is controlled based on the operational state of the transistor. During normal operation, the second gate is biased to enable fast charging current flow. During idle or off states, the second gate voltage is adjusted to suppress leakage current. This feedback-based voltage control allows the system to achieve high charging speeds when needed while minimizing leakage current during non-operational periods, resolving the contradiction between speed and leakage.
Data Source
AI summary
A display substrate, a manufacturing method therefor, and a display device are provided. The display substrate includes a base substrate and at least one transistor disposed on the base substrate, with a transistor including an active layer pattern disposed on the base substrate; a first source-drain electrode disposed on the base substrate and electrically connected with the active layer pattern; a first gate electrode disposed on a side of the active layer pattern away from the base substrate, the first gate electrode and the active layer pattern having overlapped orthographic projections on the base substrate and are not in contact with each other; a second source-drain electrode disposed on a side of the active lay pattern away from the base substrate and including a first sub-electrode and a second sub-electrode connected with each other, the second sub-electrode is located on a side of the first sub-electrode close to the first gate electrode, the first sub-electrode is electrically connected with the active layer pattern, the second sub-electrode and the active layer pattern have overlapped orthographic projections on the base substrate and are not in contact with each other.