Display Transistor Active-Layer Thickness Tuning for Low Off-Current
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Solution Overview
Problem
Existing display devices face challenges in improving the characteristics of driving and switching transistors, as their thicknesses are often similar, leading to compromised performance in hysteresis, ΔDR, and off-current levels, which affects the overall display quality.
Innovation Solution
The display device incorporates a substrate with a buffer layer and active patterns of different thicknesses, where the second active pattern has a thickness smaller than the first, allowing for distinct transistor characteristics by forming polycrystalline silicon patterns and gate electrodes, and utilizing a method that includes partial etching and laser crystallization of amorphous silicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the thickness of active patterns is made uniform for both driving and switching transistors, then the manufacturing process is simplified, but the transistor characteristics (hysteresis, ΔDR, off-current) are compromised
Solution Approach 1:
The patent applies local quality by creating different thicknesses of the active pattern for different transistor regions. Specifically, the first active pattern (for driving transistor) has a first thickness while the second active pattern (for switching transistor) has a second thickness smaller than the first thickness. This allows each transistor to have optimized characteristics for its specific function while maintaining a uniform manufacturing process using a single etching step with anisotropic properties.
2Reliability
If the thickness of the second active pattern is reduced to improve switching transistor off-current, then the off-current is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent replaces the conventional isotropic etching mechanical process with an anisotropic etching process that exhibits direction-dependent etching rates. This substitution allows the etching depth to be precisely controlled by the etching conditions rather than requiring extremely precise mask alignment, thereby achieving the required thickness difference (first thickness greater than second thickness) with relaxed manufacturing precision requirements.
3Reliability
If different thicknesses are used for first and second active patterns to optimize transistor performance, then hysteresis and ΔDR are improved, but the device complexity increases
Solution Approach 1:
The patent merges multiple functions into a single etching process step. By utilizing the anisotropic properties of the etching solution, the process simultaneously creates the thickness difference between the first and second active patterns, forms the side surfaces with specific orientations, and defines the pattern geometry all in one step. This merging approach achieves the desired structural complexity without proportionally increasing the number of manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the hysteresis and ΔDR of the driving transistor while reducing the off-current of the switching transistor, thereby improving the overall performance and reducing instantaneous afterimages and power consumption.
Implementation Method 1
crystallizing the amorphous silicon layer to form a polycrystalline silicon layer
Implementation Method 2
partially etching the second region of the amorphous silicon layer, crystallizing the amorphous silicon layer to form a polycrystalline silicon layer
Data Source
AI summary
A display device may include a substrate, a buffer layer on the substrate, a first active pattern on the buffer layer, the first active pattern having a first thickness, a second active pattern on the buffer layer spaced from the first active pattern and having a second thickness smaller than the first thickness, a first gate insulating layer on the first active pattern and the second active pattern, a first gate electrode on the first gate insulating layer, the first gate electrode overlapping the first active pattern, and a second gate electrode on the first gate insulating layer, the second gate electrode overlapping the second active pattern.