Display Data Transmitter Buffer Gating for Lower Interface Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing electronic devices face challenges in reducing power consumption, particularly in processor designs where unused components continue to consume dynamic power due to unnecessary clock and voltage provisioning.
Innovation Solution
The processor incorporates a data transmitter with a phase locked loop, clock and data blocks, voltage regulators, and buffers that are activated or deactivated based on interface modes, ensuring that only necessary components receive clocks and voltages, thereby minimizing power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If all buffers are activated to support multiple interface modes, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic buffer activation where the first buffer and second buffers are selectively enabled or disabled based on the detected interface mode. In first interface mode, all buffers are activated to support full functionality. In second interface mode, the first buffer and selected second buffers are deactivated while only necessary buffers remain active, thereby reducing power consumption while maintaining adaptability across different interface modes.
2Reliability
If clocks are provided to all blocks, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by providing clock signals selectively to specific blocks based on their operational status. The clock block receives clocks from the phase locked loop and distributes them only to active data blocks. In second interface mode, clock signals are provided only to necessary data blocks while unused blocks receive no clocks, ensuring reliable operation of active components while eliminating unnecessary power consumption in inactive blocks.
3Reliability
If voltages are provided to all blocks, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements selective voltage provisioning where the voltage regulator provides voltage signals only to blocks that are currently active. In first interface mode, voltage is supplied to all blocks including clock block and all data blocks. In second interface mode, voltage is provided only to necessary blocks while unused blocks are deprived of voltage supply, thereby maintaining reliable operation of active components while significantly reducing overall power consumption.
4Productivity
If all data lanes are used, then data transmission capacity is improved, but device complexity increases
Solution Approach 1:
The patent implements dynamic lane configuration where data blocks are selectively activated based on the interface mode. In first interface mode, all data blocks and their corresponding data lanes are activated to provide maximum data transmission capacity. In second interface mode, only necessary data blocks are activated with their corresponding lanes, while unused data blocks are deactivated, thereby reducing device complexity and power consumption while maintaining adequate transmission capacity for the specific interface requirement.
Data Source
AI summary
An electronic device includes a host processor including a data transmitter, a driving driver, and a display panel. The data transmitter includes a phase locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receives the second clock, a first buffer connected between the phase locked loop and the clock block, and a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks, and the first buffer and each of the plurality of second buffers may be activated or deactivated depending on an interface mode.