Display Apparatus Vertical Drive Circuit Bank Initialization
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Solution Overview
Problem
Existing display apparatuses with memory-in-pixel (MIP) technology face challenges in initializing pixel memories at startup, leading to unstable writing of signal values due to increased load on output circuits, especially when the number of pixels is high, resulting in incomplete initialization within the required time frame.
Innovation Solution
The display apparatus incorporates a vertical drive circuit with delay circuits and initialization control circuits that sequentially delay and control gate signals to enable simultaneous initialization of multiple pixels, reducing the load on output circuits and allowing for stable initialization within a shorter time frame.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a low level or high level value is written into the memories of the pixels simultaneously at startup, then the initialization process is completed quickly, but the load on the output circuit increases and the writing becomes unstable
Solution Approach 1:
The pixel array is divided into multiple banks (first bank and second bank), and initialization is performed sequentially on each bank rather than simultaneously on all pixels. This segmentation reduces the instantaneous load on the output circuit while maintaining fast overall initialization through parallel bank processing.
2Quantity of substance
If the number of pixels is increased to achieve high-definition display, then the display resolution is improved, but the load on the output circuit increases and stable writing becomes difficult
Solution Approach 1:
The large number of pixels is organized into multiple banks that can be processed independently. This allows high-definition displays with large pixel counts to be initialized without overwhelming the output circuit, as each bank is handled with manageable load.
Solution Approach 2:
The system dynamically switches between different initialization modes: simultaneous initialization for normal operation and sequential bank-by-bank initialization when the number of pixels exceeds a threshold. This dynamic adaptation maintains writing stability across different display resolutions.
3Reliability
If one frame time is required to initialize memories row by row in synchronization with clock signal, then the writing stability is maintained, but the initialization time becomes too long for practical applications
Solution Approach 1:
Instead of processing all pixels sequentially row by row within one frame time, the pixel array is segmented into banks that can be processed in parallel. This reduces the total initialization time while maintaining stable writing through controlled sequential access within each bank.
Solution Approach 2:
The initialization process uses periodic clock signals to control the sequential writing to each bank in a systematic manner, ensuring stable writing while completing the process in a fraction of the original frame time.
Data Source
AI summary
According to an aspect, a display apparatus includes: a plurality of pixels each of which includes a memory for storing a signal; a plurality of image signal lines each of which is configured to supply the signal; a plurality of switches each of which is included in a corresponding one of the pixels and couples a corresponding one of the image signal lines to the memory of the corresponding one of the pixels; a plurality of gate signal lines; a plurality of logic circuits coupled in series, the logic circuit at a most upstream stage being configured to receive a control signal, and each of the logic circuits being configured to output an output signal; and a plurality of control circuits each of which is configured to output a gate signal to a corresponding one of the gate signal lines based on the control signal or the output signal.