Display Panel Via-Hole Structure for High-PPI Wire Layout

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Solution Overview

Problem

Conventional display panel manufacturing processes face challenges in achieving ultra-high pixel density and sub-micron-scale device size due to limitations in via hole taper angles and increased metal wire coverage, which hinder efficient wire layout.

Innovation Solution

The display panel design includes via holes with sidewalls angled between 85 to 90 degrees, conductive filling portions, and open slots to connect metal layers, ensuring precise alignment and reduced area occupation, thereby facilitating micro thin film transistor fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the via hole taper angle is reduced to achieve smaller via hole openings, then the area occupied by the via hole opening is reduced, but the metal wire width must be increased to completely cover the via hole, which increases the line width and hinders wire layout in high PPI displays

Engineering Contradiction:
Improvevia hole opening areaVSAvoidmetal wire line width
Core Design Contradiction:
Area of stationary objectVSLength of moving object

Solution Approach 1:

The patent changes the geometric parameters of the via hole by increasing the taper angle to 85-90 degrees, which fundamentally alters the relationship between via hole opening size and metal wire coverage requirements. This parameter change enables the metal wire to cover the via hole with minimal width increase, resolving the contradiction between reducing via hole area and maintaining wire layout efficiency.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the line width and line space are reduced to achieve ultra-high pixel density, then the PPI is improved, but the via hole depth and metal wire thickness must be increased to maintain electrical connection reliability

Engineering Contradiction:
Improvepixel densityVSAvoidvia hole depth control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by optimizing the via hole taper angle to 85-90 degrees, which allows for deeper via holes while maintaining controlled opening dimensions. This enables the structure to accommodate increased via hole depth requirements for high PPI displays without compromising manufacturing precision or electrical connection reliability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the metal wire thickness is increased to completely cover the via hole with small taper angles, then the via hole coverage is improved, but the line width increases which is not conducive to wire layout in high PPI displays

Engineering Contradiction:
Improvevia hole coverageVSAvoidwire layout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the via hole geometry parameter (taper angle) to 85-90 degrees, which fundamentally improves via hole coverage efficiency. This allows thin metal wires to completely cover the via hole openings without requiring increased wire thickness, thereby maintaining simple wire layout suitable for high PPI displays while ensuring reliable via hole coverage.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12588285B2Display panel and mobile terminal
Publication Date: 2026.03.24 WUHAN CHINA STAR OPTOELECTRONICS TECH CO LTD
  • US12588285B2 patent drawing
  • US12588285B2 patent drawing
  • US12588285B2 patent drawing

AI summary

The present disclosure provides a display panel and a mobile terminal, the display panel includes a substrate and a thin film transistor layer, the thin film transistor layer including a semiconductor layer, an insulating layer and a first metal layer, the insulating layer being disposed on the substrate and the semiconductor layer and covering the semiconductor layer, the first metal layer being disposed on the insulating layer, the insulating layer including at least one via hole, the first metal layer being connected to the semiconductor layer through the via hole, and an included angle between a sidewall of the via hole and a bottom surface of the insulating layer being greater than or equal to 85 degrees and less than or equal to 90 degrees.