Display Substrate Via Overlap Structure for Stable Pixel Charging
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Solution Overview
Problem
Display substrates using oxide semiconductors face issues with insufficient charging of pixel electrodes due to anti-conduction in conductive regions exposed to air, leading to increased connection resistance and reduced performance.
Innovation Solution
The display substrate design includes a specific via hole configuration that connects the first conductive electrode with the active layer in a lapping mode, ensuring the conductive region is not exposed during etching, and optionally incorporates an auxiliary barrier layer to protect underlying film layers, reducing connection resistance and improving charging current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the conductive region is exposed to air during etching, then the via hole can be formed to connect electrodes, but anti-conduction occurs in the exposed conductive region leading to increased connection resistance
Solution Approach 1:
The patent applies preliminary action by forming a protective film layer over the conductive region before the etching process. This protective film prevents the conductive region from being exposed to air during via hole formation, thereby avoiding anti-conduction issues. The protective film is removed only after the via hole is successfully formed, ensuring the conductive region remains protected throughout the critical etching operation.
Solution Approach 2:
The protective film acts as an intermediary element between the conductive region and the etching environment. It mediates the interaction by providing a barrier that prevents direct exposure of the conductive region to air and etching chemicals, thus eliminating the harmful anti-conduction effect while allowing the via hole to be formed through the protective film.
2Ease of manufacture
If oxide semiconductor technology is used to reduce cost, then manufacturing cost decreases, but performance issues arise due to anti-conduction in exposed regions
Solution Approach 1:
The protective film is applied in advance to oxide semiconductor-based conductive regions before any processing that might expose them. This preliminary protection enables the use of cost-effective oxide semiconductor technology while preventing the performance-degrading anti-conduction effect that would otherwise occur during subsequent manufacturing steps.
Solution Approach 2:
The patent converts the potential harm of air exposure (which causes anti-conduction) into a benefit by using the protective film to create a controlled environment. The protective film transforms the harmful interaction between air and exposed conductive regions into a beneficial protected state, allowing oxide semiconductor technology to deliver its cost advantages without suffering from its susceptibility to air exposure.
3Reliability
If the via hole is positioned to connect electrodes, then electrical connection is achieved, but the conductive region becomes exposed and charging current is reduced
Solution Approach 1:
The protective film is applied before via hole formation to prevent conductive region exposure. This preliminary protection ensures that when the via hole is formed to achieve electrical connection, the conductive region remains covered, thereby maintaining optimal charging current levels while still achieving the necessary electrical connectivity.
Data Source
AI summary
A display substrate, display panel, and display device. The display substrate comprises an active layer, a first insulating layer, a first metal layer, a second insulating layer, and a first conductive electrode sequentially arranged on a base; the first metal layer comprises a gate and a first electrode; the portion, exposed through a first via hole formed in the first insulating layer, of the active layer comprises first and second sub-portions; the first electrode is in lap joint with the first sub-portion by the first via hole; a second via hole is formed in the second insulating layer and located on the side, distant from the gate, of a partition boundary of the first and second sub-portions; orthographic projections of the second via hole and the first electrode on the base partially overlap; and the first conductive electrode is connected to the first electrode by the second via hole.


