Display Substrate Shift Register Topology for Narrow-Border Layout
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Solution Overview
Problem
Existing display substrates face challenges in optimizing the layout and connection of shift register units, leading to space congestion and signal interference, which affects the display quality and makes it difficult to achieve a narrow frame design.
Innovation Solution
The display substrate incorporates a shift register unit with a specific arrangement of transistors and clock signal lines, including a first and second clock signal line, input circuit, output circuit, control circuits, and noise reduction transistors, optimized to reduce the length and width of the shift register unit, thereby minimizing space congestion and signal interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the shift register unit uses a conventional layout arrangement, then the connection between transistors is simplified, but the area occupied by the shift register unit increases and space congestion occurs
Solution Approach 1:
The patent changes the layout arrangement from a conventional linear arrangement to a specific two-dimensional arrangement where the first and second noise reduction transistors are positioned adjacent to the first and second control transistors respectively. This spatial reorganization in another dimension reduces the overall area while maintaining connection simplicity through the intermediate transfer electrode.
Solution Approach 2:
The patent employs a nested structure where the intermediate transfer electrode is positioned between the control transistors and noise reduction transistors, creating a compact nested arrangement. The gate electrode of the first noise reduction transistor connects to the first electrode of the first control transistor through this intermediate transfer electrode, forming a nested connection pattern that reduces area occupation.
2Area of stationary object
If the shift register unit uses a compact layout to reduce area, then space congestion is reduced, but the connection complexity between transistors increases
Solution Approach 1:
The patent introduces an intermediate transfer electrode as a mediator between the control transistors and noise reduction transistors. This intermediate element simplifies the connection by providing a direct pathway through the intermediate transfer electrode, avoiding complex multi-layer connections that would otherwise be required in a compact layout.
3Ease of operation
If the clock signal lines are arranged conventionally, then the signal transmission is straightforward, but parasitic capacitance increases and signal interference occurs
Solution Approach 1:
The patent applies local quality by making the first and second clock signal lines extend along the first direction specifically in the region where the active layers are arranged. This localized arrangement reduces parasitic capacitance in the critical area where transistors are positioned, while maintaining straightforward signal transmission through the clock signal lines.
Data Source
Figure 1A
Figure 1B~1C
Figure 1D~2A
AI summary
Provided are a display substrate and a method for manufacturing same, and a display apparatus. The display substrate comprises: a base substrate, and a shift register unit and a first clock signal line that are arranged on the base substrate, wherein the first clock signal line extends on the base substrate in a first direction; and the shift register unit comprises an input circuit, an output circuit, a first control circuit, a second control circuit and an output control circuit. The orthographic projection of an intermediate via electrode on the base substrate is located between the orthographic projection, on the base substrate, of an active layer of a first control transistor and an active layer of a second control transistor and the orthographic projection, on the base substrate, of an active layer of a first noise-reduction transistor and an active layer of a second noise-reduction transistor, wherein a gate electrode of the first noise-reduction transistor is connected to a first electrode of the first control transistor and a first electrode of the second control transistor by means of the intermediate via electrode. In the display substrate, the layout of a line structure is optimized, thereby facilitating the implementation of a narrow-border design of a display panel.