Display Wiring Layout for Large 4K/8K Panels With Low-Mobility TFTs

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Solution Overview

Problem

High-resolution display devices with large screen sizes face challenges in operating at high driving frequencies due to increased load on transistors, especially when field-effect mobility is low, requiring a solution that enhances productivity, reliability, and cost-effectiveness while supporting amorphous silicon or metal oxide technologies.

Innovation Solution

The display device incorporates a unique wiring configuration with multiple source lines and conductive layers, allowing for efficient signal distribution and reduced parasitic capacitance, along with a manufacturing method that includes specific steps for forming gate lines, insulating layers, and pixel electrodes, enabling high-resolution displays with low field-effect mobility transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the resolution and screen size of the display device are increased, then the display quality is improved, but the load on the transistor increases making high-frequency operation difficult

Engineering Contradiction:
Improvedisplay resolutionVSAvoidtransistor operation stability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The display device is divided into multiple independent scanning regions (first scanning region and second scanning region) with separate gate lines and transistor sets. This segmentation allows each region to be driven independently at high frequency, reducing the overall load on individual transistors while maintaining high resolution across the entire large screen.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If amorphous silicon is used for the semiconductor film, then manufacturing cost is reduced, but field-effect mobility is low limiting high-frequency operation

Engineering Contradiction:
Improvemanufacturing costVSAvoidfield-effect mobility
Core Design Contradiction:
Ease of manufactureVSSpeed

Solution Approach 1:

The display is divided into multiple scanning regions allowing the use of amorphous silicon transistors with lower field-effect mobility in each segment, while the overall high-frequency operation is achieved through parallel scanning of multiple regions. This enables cost-effective amorphous silicon manufacturing to achieve performance previously requiring expensive high-mobility materials.

Inventive Principle:
Principle #1Segmentation

3Measurement precision

If the number of transistors is increased for high-resolution displays, then display quality is improved, but manufacturing complexity and cost increase

Engineering Contradiction:
Improvedisplay resolutionVSAvoidtransistor quantity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

By dividing the display into multiple scanning regions with shared source and drain lines, the patent reduces the total number of transistors required compared to a conventional single-scanning-region design. Each region uses a subset of the total transistor count, and regions are scanned sequentially, achieving high resolution with reduced manufacturing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Source and drain lines serve multiple functions by being shared across multiple scanning regions. The same source line and drain line structures are reused in different regions, reducing the total number of conductive elements needed and simplifying the manufacturing process while maintaining high display resolution.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12154909B2Display device and manufacturing method thereof
Publication Date: 2024.11.26 SEMICON ENERGY LAB CO LTD
  • US12154909B2 patent drawing
  • US12154909B2 patent drawing
  • US12154909B2 patent drawing

AI summary

A display device that is suitable for increasing its size is provided. The display device includes first to third wirings, a first transistor, first to third conductive layers, and a first pixel electrode; the first wiring extends in a first direction and intersects with the second and the third wirings; the second and the third wirings each extend in a second direction intersecting with the first direction; a gate of the first transistor is electrically connected to the first wiring; one of a source and a drain of the first transistor is electrically connected to the second wiring through the first to the third conductive layers; the second conductive layer includes a region overlapping with the third wiring; the first conductive layer, the third conductive layer, and the first pixel electrode contain the same material; the first wiring and the second conductive layer contain the same material; the first wiring is supplied with a selection signal; and the second and the third wirings are supplied with different signals.