Display Writeback Segmentation for High-Resolution Bandwidth Limits

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Solution Overview

Problem

High-resolution or ultrahigh-resolution graphical content processing faces bandwidth limitations due to high pixel transfer rates exceeding circuitry and processor capabilities.

Innovation Solution

A multi-pipe/plane combiner (MPC) circuitry module splits high-resolution graphical frames into spatially segmented portions for parallel processing by multiple display pixel processing (DPP) pipelines, combining the processed portions to reduce bandwidth requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If high-resolution graphical content is processed through a single display pixel processing pipeline, then processing quality is maintained, but bandwidth requirements exceed hardware limitations

Engineering Contradiction:
Improveprocessing qualityVSAvoidbandwidth requirements
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent divides the high-resolution graphical frame into multiple spatial segments (e.g., left and right halves for 8K resolution) and processes each segment through a separate display pixel processing pipeline. This segmentation reduces the bandwidth requirement for each individual pipeline while maintaining overall processing quality through parallel processing and combination of the segmented portions.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If graphical frames are spatially segmented for parallel processing, then bandwidth requirements are reduced, but processing complexity increases

Engineering Contradiction:
Improvebandwidth requirementsVSAvoidprocessing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent combines multiple processed spatial segments back together to form the complete high-resolution graphical frame. The combiner module merges the output from multiple display pixel processing pipelines, reducing the overall processing complexity compared to handling the entire frame through a single pipeline while maintaining the bandwidth benefits of parallel processing.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If multiple DPP pipelines process spatially segmented portions in parallel, then processing speed increases, but coordination complexity increases

Engineering Contradiction:
Improveprocessing speedVSAvoidcoordination complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a combiner module as an intermediary that receives processed spatial segments from multiple display pixel processing pipelines and combines them into the final output. This intermediary simplifies the coordination complexity by providing a centralized point for merging results, allowing parallel pipelines to operate independently while maintaining synchronized output through the combiner's coordination.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12482054B2Multi-pass writeback with single-pass display consumption
Publication Date: 2025.11.25 ATI TECHNOLOGIES ULC
  • US12482054B2 patent drawing
  • US12482054B2 patent drawing
  • US12482054B2 patent drawing

AI summary

Techniques described herein allow multi-pass writeback processing of graphical frames (such as those having a high or ultrahigh resolution) to reduce bandwidth for display operations by, for example, splitting an input stream for processing by separate graphical pipelines as two or more spatially segmented portions. After receiving a graphical frame for processing, the graphical frame is spatially segmented into multiple portions. Each of the multiple portions is provided to a respective graphical pipeline of a plurality of graphical pipelines for processing. Each processed portion of the graphical frame is written substantially simultaneously to a corresponding portion of a system memory.