DisplayPort Link Power Management Using In-Band LFPS Signaling
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Solution Overview
Problem
Current DisplayPort specifications lack link power management mechanisms, and existing Advanced Link Power Management (ALPM) techniques require tight coupling between the main link and the AUX interface, which is unmanageable in complex display topologies, leading to high latency and inefficiency in power management.
Innovation Solution
Implementing Low Frequency Periodic Signaling (LFPS) over the main link for both DisplayPort and Embedded DisplayPort topologies, allowing devices to transition into and out of power states without relying on the AUX interface, reducing latency and enabling unified power management across different display configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If ALPM technique uses wake signaling over AUX interface, then link power management can be implemented, but tight coupling between main link and AUX interface makes it unmanageable in complex display topologies
Solution Approach 1:
The patent extracts the power management signaling from the AUX interface and places it directly on the main link using LFPS. This separation allows the main link to independently manage power states without requiring coordinated handshaking through the AUX interface, thereby reducing the tight coupling and improving adaptability to complex topologies with multiple devices.
Solution Approach 2:
The main link is given dual functionality: it serves both as the primary data transmission channel and as the control channel for power management signaling. By embedding LFPS packets within the main link's training and maintenance sequences, the system eliminates the need for a separate AUX interface for power management, simplifying the overall architecture and improving versatility across different display topologies.
2Loss of time
If ALPM uses AUX interface handshaking, then power management is achieved, but latency increases due to the handshake process
Solution Approach 1:
The patent implements preliminary power management actions by embedding LFPS signaling within the existing main link training sequences. Instead of waiting for AUX interface handshaking to initiate power transitions, the source device can pre-signal link power management commands during link training or maintenance phases, allowing sink devices to prepare for state transitions in advance and reducing overall latency.
Solution Approach 2:
The patent skips the intermediate AUX interface handshaking steps by directly transmitting power management commands over the main link using LFPS packets. This eliminates the sequential delays associated with AUX channel arbitration, command transmission, and acknowledgment, allowing power state transitions to occur more rapidly through the high-speed main link.
3Loss of energy
If DisplayPort lacks link power management mechanisms, then the interface remains simple, but power efficiency is poor
Solution Approach 1:
The patent merges power management functionality with the existing DisplayPort main link infrastructure by utilizing LFPS packets that are already part of the DisplayPort protocol specification. Instead of adding a completely separate power management subsystem, the solution combines power control signaling with the existing link training and maintenance sequences, achieving power efficiency without proportionally increasing system complexity.
Solution Approach 2:
The DisplayPort link is made self-managing for power operations by enabling the source and sink devices to autonomously negotiate and execute power state transitions through LFPS signaling. The devices use built-in logic to interpret LFPS packets and automatically perform link power management without requiring external controller intervention, thereby improving power efficiency while minimizing the need for additional complex control circuitry.
Data Source
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AI summary
An apparatus includes a port comprising circuitry to couple the apparatus to one or more devices over a DisplayPort (DP)-based link and a processor to generate signals for communication over the DP-based link. The apparatus also includes memory with instructions to cause the processor to initiate a transition to a low power state in devices of the DP-based link by transmitting a sleep pattern signal over the DP-based link, and initiate a transition to an active power state in devices of the DP-based link by transmitting a wake pulse sequence and physical link establishment signal pattern over the DP-based link. The transition to active power state comprises a wake-up pulse sequence (410), a PHY link establishment signal pattern (420) and a clock and data switch CDS signal pattern (430) followed by the video signal. The CDS enables the LTTPR to be trained so as to obtain a seamless communication between the DP-TX and the DP-RX.