DisplayPort Receiver Clocking for Low-Resolution Power Reduction
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Solution Overview
Problem
The high power consumption of DisplayPort standards at midrange and low resolution settings poses a challenge for adoption in portable devices, where available power is limited, often leading manufacturers to avoid using DisplayPort due to battery life concerns.
Innovation Solution
The method involves using an auxiliary channel to send a low-speed reference clock in an Information Handling System (IHS), which reduces power consumption by allowing the DisplayPort link to operate at speeds lower than the standard 2.7 Gbps and 1.62 Gbps, similar to LVDS or HDMI, thereby minimizing unnecessary power drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DisplayPort standard is used for midrange and low resolution settings, then display interface performance is improved, but power consumption increases significantly
Solution Approach 1:
The patent implements dynamic clock speed adjustment in the DisplayPort link, allowing the system to operate at lower clock speeds for midrange and low resolution settings rather than being locked into high fixed speeds. This enables the DisplayPort interface to adapt its performance characteristics to match the actual resolution requirements, reducing power consumption when full DisplayPort performance is not needed.
Solution Approach 2:
The patent changes the operational parameters of the DisplayPort receiver by introducing an alternative clocking mode that operates at lower speeds. By modifying the clock speed parameter from the standard high speeds (2.7 Gbps, 1.62 Gbps) to lower speeds appropriate for midrange and low resolutions, the system achieves significant power savings while maintaining functional performance.
2Speed
If DisplayPort link operates at standard high speeds, then data transmission capability is improved, but unnecessary power drain occurs at lower resolutions
Solution Approach 1:
The patent applies partial action by operating the DisplayPort link at reduced clock speeds that are sufficient for midrange and low resolution settings but lower than the maximum capability. This partial operation mode provides just enough data transmission speed for the current resolution requirements without the excessive power consumption associated with always operating at maximum speed.
3Adaptability or versatility
If DisplayPort is adopted in portable devices, then display interface versatility is improved, but battery life is reduced due to high power consumption
Solution Approach 1:
The patent enables the DisplayPort interface to dynamically adjust its operational characteristics based on the connected display's resolution requirements. By implementing lower clock speed modes, the system maintains the versatility of DisplayPort adoption in portable devices while reducing power consumption to acceptable levels for battery-operated equipment.
Data Source
AI summary
A method for reducing power consumption in an information handling system (IHS) where the method includes receiving main data through a main link, wherein the main link provides at least one data lane. The IHS also receives a reference clock corresponding to the main data through an auxiliary channel and provides the reference clock to a first phase-lock loop, wherein the first phase-lock loop outputs a stream clock.