Disposable Test Circuitry in Scribe Lanes for Semiconductor Bond Pads
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Solution Overview
Problem
The integration of self-test circuitry within semiconductor die increases die and package size and poses risks due to externally accessible test connection pads, which can lead to misuse and ESD/latch-up requirements, while also causing wire bond delamination and ILD cracking issues during processing.
Innovation Solution
Disposable test circuitry is formed within scribe lanes, with trenches filled or lined with dielectric/conductive material, and connection route lines are formed to connect device circuitry to bond pads, allowing for encapsulation and protection without seal rings, reducing the need for external test pads and minimizing stress on bond pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If self test circuitry is included within the semiconductor die, then test cycle time is improved, but die area increases and package size increases
Solution Approach 1:
The patent divides the test circuitry into two parts: essential test functions remain on-chip while non-essential test functions are moved to external test circuitry located off-chip. This segmentation allows the die area to be reduced by removing unnecessary on-chip test components while still maintaining efficient test capabilities through the combination of on-chip and off-chip test resources.
2Loss of time
If self test circuitry is included within the semiconductor die, then test cycle time is improved, but package size increases
Solution Approach 1:
The patent extracts non-essential test circuitry functions from the semiconductor die and places them in external test circuitry. This extraction reduces the die area required for test functions, which in turn reduces the overall package size while maintaining comprehensive test capabilities through the external test resources.
3Ease of operation
If externally accessible test connection pads are provided, then test procedures can be performed, but customer misuse can occur leading to device failures
Solution Approach 1:
The patent implements disposable test circuitry that is formed in the scribe lane and is discarded during the singulation process. This disposable approach allows test functions to be accessible during manufacturing testing while preventing customer access to test pads after the product is finalized, thereby eliminating the risk of customer misuse while maintaining test capabilities during production.
4Ease of operation
If externally accessible test connection pads are provided, then test procedures can be performed, but ESD and latch-up requirements must be met
Solution Approach 1:
By implementing test circuitry that is disposable and discarded during singulation, the patent eliminates the need for permanent external test pads in the final product. This approach maintains test accessibility during manufacturing while removing the complexity of meeting ESD and latch-up requirements for external test pins in the customer-facing product.
5Ease of operation
If wirebonding is used to connect bond pads, then external connections are established, but wire bond delamination or ILD cracking can occur
Solution Approach 1:
The patent modifies the physical parameters of the bond pad structure by forming recesses in the interlayer dielectric and positioning bond pads within these recesses. This parameter change in the bond pad geometry reduces the stress concentration during wirebonding and pillar attachment processes, thereby preventing wire bond delamination and ILD cracking while maintaining connection capability.
6Strength
If pillar connections are used to attach die, then die to substrate attachment is achieved, but excessive stress on bond pad can cause pad delamination or ILD cracking
Solution Approach 1:
The patent changes the geometric parameters of the bond pad structure by creating recesses in the interlayer dielectric and positioning bond pads within these recesses. This parameter modification reduces stress concentration during pillar attachment and thermal cycling, thereby preventing pad delamination and ILD cracking while maintaining strong die attachment.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the size of the semiconductor package, minimizes the risk of customer misuse, and decreases the likelihood of wire bond delamination and ILD cracking by eliminating the need for external test pads and reducing stress on bond pads, thereby enhancing the reliability and efficiency of semiconductor manufacturing.
Implementation Method 1
subjected to ultrasonic generation (USG). The vibration of the USG effectively scrubs the FAB against the aluminum bond pad, promoting interdiffusion of the metal of the FAB and the metal of the bond pad
Implementation Method 2
a free air ball (FAB) is formed at the end of wire by electrical flame-off that heats the end of wire to a malleable state
Data Source
AI summary
An integrated circuit die includes a first bond pad having a bond contact area at a first depth into a plurality of build-up layers over a semiconductor substrate of the integrated circuit die, having sidewalls that surround the bond contact area, the sidewalls extending from the first depth to a top surface of the plurality of build-up layers, and having a top portion that extends over a portion of a top surface of the plurality of build-up layers.