Disposable Test Circuitry in Scribe Lanes for Semiconductor Die
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Solution Overview
Problem
The integration of self-test circuitry within semiconductor device dies increases die and package sizes and poses risks due to externally accessible test connection pads, which can lead to misuse and require meeting stringent ESD and latch-up requirements.
Innovation Solution
Disposable test circuitry is formed within scribe lanes during semiconductor processing, allowing for testing and subsequent removal, reducing die area and eliminating the need for external test pads by encapsulating the edges with a protective metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If self-test circuitry is integrated within the semiconductor device die, then test cycle time is improved, but die area increases and package size increases
Solution Approach 1:
The test circuitry is segmented from the main device die and placed in the scribe lane area, allowing the die to be divided into functional device regions and separate test regions. This segmentation enables testing functionality without increasing the active device die area, as the test circuitry occupies the otherwise wasted scribe lane space between adjacent dies.
Solution Approach 2:
The test circuitry is relocated from the two-dimensional plane of the device die to the scribe lane dimension, utilizing the peripheral area surrounding the dies on the wafer. This dimensional relocation allows test functionality to be added without consuming valuable die area, effectively using the 'negative space' between devices.
2Loss of time
If self-test circuitry is integrated within the semiconductor device die, then test cycle time is improved, but externally accessible test connection pads are required which can lead to misuse
Solution Approach 1:
The test connection pads and test circuitry are extracted from the device die and relocated to the scribe lane area. This extraction removes the harmful element (externally accessible test pads that can be misused) from the device footprint, eliminating the risk of customer misuse while preserving the beneficial testing functionality in a controlled manufacturing-only environment.
Solution Approach 2:
The test circuitry in the scribe lane is designed as disposable test structures that are used during manufacturing and then discarded when the die are singulated. These temporary test structures serve their purpose during fabrication and testing, then are removed, leaving no permanent test access points that could be misused by customers.
3Reliability
If test circuitry is included within the semiconductor die, then test procedures can be performed, but ESD and latch-up requirements for external pins must be met
Solution Approach 1:
The test circuitry and its connection pads are extracted from the device die structure and placed exclusively in the scribe lane region. This extraction eliminates the need for test pads to appear as external pins on the packaged device, thereby removing the requirement to meet ESD and latch-up specifications for external pins, while test capability is preserved in the manufacturing environment.
4Area of stationary object
If scribe lane space is used for test circuitry, then die area is reduced, but additional processing steps are required
Solution Approach 1:
The test circuitry formation process is merged with the existing scribe lane fabrication steps. By combining test structure creation with the standard scribe lane processing that already occurs during manufacturing, additional complex steps are avoided. The test circuitry is formed using the same deposition, patterning, and etching processes that are already applied to create the scribe lane infrastructure.
Solution Approach 2:
The scribe lane structure is given multiple functions: it serves both as the traditional mechanical separation region between dies and as the hosting environment for test circuitry. This multi-functionality allows the existing scribe lane infrastructure to dual-purpose, accommodating test structures without requiring separate dedicated test areas or additional manufacturing complexity.
Data Source
AI summary
Embodiments are disclosed for semiconductor manufacturing using disposable test circuitry formed within scribe lanes. The manufacturing steps can include forming device circuitry within a semiconductor die and forming test circuitry within a scribe lane. One or more electrical connection route lines are also formed that connect the device circuitry and test circuitry blocks. Further, each die can be connected to a single test circuitry block, or multiple dice can share common test circuitry blocks. After testing, the electrical connection route line(s) are sealed, and the test circuitry is discarded when the device dice are singulated. For certain embodiments, the edge of the devices dice are encapsulated with a protective metal layer, and certain other embodiments include protective sealrings through which the connection route lines pass to enter the dice from the test circuitry blocks within the scribe lanes.