Distributed ADC Architecture With Delay Lines for Wideband Sampling
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Solution Overview
Problem
Current analog to digital converters (ADCs) face challenges in achieving high bandwidth and dynamic range, particularly due to bandwidth bottlenecks when driving ADC loads and managing input and clock signal impedances, which limits their performance in applications requiring wide spectral coverage and high information processing.
Innovation Solution
A distributed ADC architecture utilizing cascaded ADC slices with programmable delay lines in both input and clock signal paths, combined with transmission lines to absorb impedance and enable time-interleaved sampling, effectively increasing bandwidth and dynamic range by allowing uniform sampling at a higher rate and summing uncorrelated noise sources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a single ADC is used to convert analog signals, then the device complexity is low, but the bandwidth and sample rate are limited
Solution Approach 1:
The patent divides a single ADC into multiple parallel ADC slices (e.g., 4 slices), each operating at a lower sample rate. By distributing the conversion task across multiple slices and combining their outputs, the system achieves an effective sample rate multiplication (e.g., 4x) while keeping each individual slice simpler and more manageable.
2Speed
If multiple ADC slices are used in parallel to increase sample rate, then the bandwidth increases, but the impedance matching becomes difficult
Solution Approach 1:
The patent introduces transmission lines as intermediary elements between the analog input signal and multiple ADC slices. These transmission lines are specifically designed with characteristic impedances that automatically absorb and match the impedances of the ADC inputs, eliminating the need for complex external impedance matching networks and simplifying the overall system design.
3Speed
If traditional impedance matching networks are used for multiple ADC inputs, then the bandwidth is limited, but the impedance matching is achieved
Solution Approach 1:
The transmission lines serve as intermediary elements that inherently provide impedance matching through their characteristic impedance properties. This eliminates the need for traditional broadband impedance matching networks, which are bandwidth-limited and require precise component values. The transmission line approach naturally accommodates a broader frequency range while maintaining impedance match.
4Speed
If the ADC input capacitance is high, then the bandwidth is limited, but the noise performance may be improved
Solution Approach 1:
By segmenting the total input capacitance requirement across multiple parallel ADC slices, each slice presents a smaller individual capacitance load to the signal source. This distributed capacitance approach allows for higher bandwidth while the parallel architecture maintains the overall noise performance through coherent signal summation and incoherent noise addition.
Data Source
AI summary
An ultra-wideband distributed ADC can be cascaded to build high performance radio frequency (RF) analog electronics integrated with advanced digital complementary metal-oxide-semiconductor (CMOS) electronics on the same wafer. Advantages can include wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. Part of an overall system includes a precise, programmable, real-time delay circuit that can achieve picosecond accuracy.