Spatially Distributed Amplifier Stages for Low-Resistance 3D Memory Routing
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Solution Overview
Problem
In integrated circuits, particularly in three-dimensional memory arrays, existing amplifier circuits face challenges with high output resistance due to tungsten interconnects and limited routing freedom, leading to difficulties in managing current distribution and voltage regulation across dense memory arrays.
Innovation Solution
The implementation of spatially distributed final amplifier stages, sharing a common control node and output node, allows for efficient current distribution and voltage regulation by enabling separate amplifier configurations for read and write operations within the same memory array, reducing output resistance and improving routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If amplifier stages are spatially distributed across a large area, then output resistance is reduced and current distribution is improved, but routing complexity and difficulty of controlling sensitive nodes increases
Solution Approach 1:
Multiple amplifier stages share a common control node and common output node, merging the control and output functions across spatially distributed stages. This reduces the number of separate routing paths needed while maintaining the benefits of spatial distribution for reducing output resistance.
Solution Approach 2:
The common control node serves all distributed amplifier stages simultaneously, and the common output node collects signals from all stages. This multi-functional approach allows a single routing path to serve multiple purposes, reducing overall routing complexity.
2Measurement precision
If multiple parallel transistors are spatially intermixed in a two dimensional array, then offset voltage is reduced due to gradient cancellation, but area utilization and routing freedom are constrained
Solution Approach 1:
The amplifier circuit is divided into multiple parallel transistor stages that are spatially separated and distributed across different regions of the chip. Each transistor group maintains the offset cancellation benefit while the spatial segmentation allows better area utilization and routing freedom.
3Object-affected harmful factors
If final amplifier stages are distributed over a wide area, then output node sensitivity to wiring resistance and noise coupling is reduced, but difficulty of detecting and measuring control nodes increases
Solution Approach 1:
All distributed amplifier stages share a common control node, merging the control function into a single accessible point. This allows easy measurement and control of the amplifier stages without requiring access to multiple distributed control points, while still maintaining low sensitivity to wiring resistance through spatial distribution.
Data Source
AI summary
An exemplary amplifier circuit includes a first group of spatially distributed final amplifier stages having a first configuration, and a second group of spatially distributed final amplifier stages having a second configuration different than the first configuration. Both groups share the same control node for their respective final amplifier stages, and both groups share the same amplifier output node. Each group is typically enabled at a time that the other is disabled. In certain embodiments incorporating a memory array, only one critical analog node must be routed throughout the memory array.