Distributed Arbiters for Digital Bus Latency Reduction
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Solution Overview
Problem
Arbitration-based allocation of shared resources in digital processing systems often results in latency issues due to the time delay between requesting a resource and receiving allocation, which becomes problematic as clock frequencies increase and die sizes grow, making it difficult to meet timing requirements.
Innovation Solution
Implementing multiple arbiters strategically placed throughout the system, where each entity sends requests to all arbiters, and the closest arbiter communicates the allocation, reducing latency by ensuring the grant indication is received within a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a single arbiter is used for resource allocation, then the system structure is simple, but the latency increases and timing requirements cannot be met at higher clock frequencies
Solution Approach 1:
The patent divides the single arbiter into multiple arbiters distributed across different locations in the system. Each arbiter handles allocation requests from nearby entities, segmenting the centralized arbitration function into distributed units. This reduces the communication distance and latency while maintaining the arbitration functionality through coordinated operation of multiple arbiters.
Solution Approach 2:
The patent transitions from a single-point (centralized) arbitration model to a multi-point (distributed) model by adding spatial dimensionality to the arbiter placement. Arbiters are positioned at multiple locations throughout the system, allowing entities to access the nearest arbiter and reducing the path length for grant signal propagation.
2Productivity
If the die size increases to accommodate more entities, then the system capacity increases, but the latency for resource allocation increases
Solution Approach 1:
As the die size increases and more entities are added, the patent segments the arbitration function into multiple distributed arbiters placed throughout the enlarged die. This ensures that no entity is too far from an arbiter, maintaining low latency even as system capacity scales up with larger die size and more entities.
Solution Approach 2:
The patent implements local arbitration by placing arbiters in strategic locations across the die, allowing each region to have local arbitration capability. Entities access nearby arbiters rather than a distant centralized arbiter, reducing the average communication distance and latency as the die size grows.
3Speed
If clock frequency increases to improve processing speed, then the system performance improves, but the timing requirements become harder to meet due to increased latency
Solution Approach 1:
By distributing arbiters across multiple locations in space, the patent reduces the maximum distance a grant signal must travel. This spatial distribution allows higher clock frequencies to be achieved because the critical path delay is reduced, providing sufficient timing margin even at increased speeds.
Data Source
AI summary
A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource.