Arithmetic Circuit Using Distributed LUTs for Bit-Position Processing
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Solution Overview
Problem
Conventional product-sum arithmetic circuits face increased circuit scale and power consumption due to the need for accurate multiplication of all bits, leading to wasteful processing of lower bits with high noise components, which are subsequently deleted by figure matching circuits.
Innovation Solution
The proposed arithmetic circuit employs distributed arithmetic, using a LUT generation circuit and distributed arithmetic circuits to perform binomial product-sum operations, invalidating lower bits at each bit position and reducing circuit area and power consumption by omitting unnecessary processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional multiplication circuits perform accurate multiplication of all bits, then arithmetic accuracy is maintained, but circuit area and power consumption increase due to processing lower bits with high noise components
Solution Approach 1:
The patent segments the multiplication process into bit-position-basis arithmetic operations, where each bit position is processed separately using LUTs (Look-Up Tables). This segmentation allows the circuit to process only significant bits for each position, eliminating the need to accurately process all lower bits that contain high noise components, thus reducing circuit area while maintaining arithmetic accuracy.
Solution Approach 2:
The patent applies local quality by making different parts of the multiplication circuit have different processing characteristics. Significant bit positions use full-precision LUT-based arithmetic, while lower bit positions with high noise components use simplified processing or are truncated. This local differentiation maintains accuracy where needed while reducing circuit area where precision is less critical.
2Measurement precision
If conventional multiplication circuits perform accurate multiplication of all bits, then arithmetic accuracy is maintained, but power consumption increases due to processing lower bits with high noise components
Solution Approach 1:
The multiplication circuit is segmented into bit-position-basis arithmetic units that process each bit position independently. This segmentation allows power consumption to be optimized by activating only the necessary LUTs and arithmetic units for each bit position, avoiding the continuous high power consumption of full-precision multiplication circuits that process all bits regardless of their significance.
Solution Approach 2:
Different bit positions are assigned different processing qualities based on their noise characteristics. Significant bit positions receive full processing resources, while lower bit positions with high noise components receive reduced processing or are truncated. This local quality differentiation reduces overall power consumption while maintaining arithmetic accuracy for significant bits.
3Area of stationary object
If figure matching circuit deletes lower bits with high noise components, then circuit area and power consumption are reduced in subsequent stages, but unnecessary processing is wasted in multiplication circuits
Solution Approach 1:
The patent performs preliminary action by truncating or simplifying lower bit processing during the multiplication stage itself, before the figure matching circuit operates. The bit-position-basis arithmetic circuits are configured to invalidate or simplify processing of lower bits with high noise components, so that subsequent figure matching and summation stages receive already-optimized inputs, eliminating wasteful processing in earlier stages.
4Area of stationary object
If distributed arithmetic with LUT generation circuit is used, then circuit area and power consumption are reduced, but processing speed may be affected
Solution Approach 1:
The LUT generation circuit performs preliminary action by pre-computing and storing multiplication results for all possible input combinations in Look-Up Tables. During actual multiplication operations, the circuit simply retrieves pre-computed values from LUTs based on input bit patterns, avoiding real-time complex calculations. This preliminary computation significantly speeds up processing while keeping the runtime circuit area small.
Solution Approach 2:
The patent uses LUTs as copies of pre-computed multiplication results. Instead of performing actual multiplication operations in the critical path, the circuit uses indexed copying of pre-stored values from LUTs. This copying mechanism replaces computationally intensive operations with simple memory access, improving processing speed while reducing the complexity and area of the arithmetic circuit.
Data Source
AI summary
An arithmetic circuit includes a LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and distributed arithmetic circuits (2-m) that calculate values z[m] that are sums of products of data x[m, n] of a data set X[m] containing M pairs of data x[m, n] and the coefficients c[n], in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes binomial distributed arithmetic circuits that, for each of the pairs, calculate sums of products of a value obtained by pairing N data x[m, n] corresponding to the circuit two by two and a value obtained by pairing the coefficients c[n] two by two, and a figure matching circuit that matches a number of decimal figures of the sums with a predetermined number of decimal figures.