Distributed Arithmetic FIR Correlator for Low-Power Signal Filtering
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Solution Overview
Problem
Conventional implementations of finite impulse response (FIR) filters require significant power consumption and occupy large space due to the need for numerous multiplier and adder stages, making them costly for signal processing systems.
Innovation Solution
The implementation of an FIR filter using a distributed arithmetic architecture, which reduces the number of high-power components and minimizes the footprint by performing bit-level rearrangement of multiplications and using logic gates instead of multipliers, resulting in a more efficient power and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MAC architecture is used to implement an FIR filter, then the filter can achieve effective frequency component attenuation, but the power consumption and footprint increase due to numerous multiplier and adder stages
Solution Approach 1:
The patent replaces the conventional MAC architecture with a distributed arithmetic (DA) architecture that uses lookup tables and adders instead of multipliers. This substitution eliminates the need for power-consuming multiplier circuits while maintaining the same filtering function, directly resolving the contradiction between reliability and power consumption.
Solution Approach 2:
The patent transforms the multiplication operation into a lookup table-based approach where pre-computed values are stored in memory. By changing the computational parameter from real-time multiplication to table lookup and addition, the power consumption is significantly reduced while maintaining filtering effectiveness.
2Reliability
If a conventional MAC architecture is used to implement an FIR filter, then the filter can achieve effective frequency component attenuation, but the footprint increases due to numerous multiplier and adder stages
Solution Approach 1:
The patent replaces the MAC architecture with a distributed arithmetic architecture that uses lookup tables and adders instead of multipliers. This substitution eliminates the need for large-area multiplier circuits while maintaining the same filtering function, directly resolving the contradiction between reliability and footprint.
Solution Approach 2:
The patent uses lookup tables that store pre-computed multiplication results. By copying these pre-computed values into memory structures, the need for complex multiplier circuits is eliminated, significantly reducing the footprint while maintaining filtering effectiveness.
3Use of energy by stationary object
If a distributed arithmetic architecture is used to implement an FIR filter, then the power consumption and footprint are reduced, but the implementation complexity increases due to bit-level rearrangement
Solution Approach 1:
The patent performs bit-level rearrangement and pre-computation of values during the design and setup phase. By preparing the lookup tables and organizing the bit-level data structures in advance, the runtime complexity is reduced, resolving the contradiction between power consumption and implementation complexity.
Data Source
AI summary
Provided herein is an implementation of a finite impulse response (FIR) filter that uses a distributed arithmetic architecture. In one or more example, a data sample with multiple bits is processed through a plurality of bit-level multiply and accumulate circuits, wherein each bit of the data sample corresponds to a bit of the data sample. The output of each bit-level multiply and accumulate circuit can then be shifted by an appropriate amount based on the bit placement of the bit of the data sample that corresponds to the bit-level multiply and accumulate circuit. After each output is shifted by the appropriate amount, the outputs can be aggregated to form a final FIR filter result.