Distributed ASISP Architecture for Wireless Signal Processing

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Solution Overview

Problem

Existing wireless communication systems face inefficiencies in process switching and computational resource management, leading to high energy consumption and overhead due to the use of general-purpose digital signal processors (DSPs, which are unsuitable for supporting multiple processes effectively.

Innovation Solution

The implementation of distributed application-specific instruction set processors (ASISPs) with a centralized controller and a novel instruction set, including a WAIT command, allows for efficient process switching and reduced power consumption by storing state information locally and coordinating processing tasks in a master/slave relationship.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If general-purpose digital signal processors (DSPs) are used to support multiple processes, then processing flexibility is improved, but process switching overhead and energy consumption increase

Engineering Contradiction:

Improveprocessing flexibilityVSAvoidenergy consumption

Core Design Contradiction:

Adaptability or versatilityVSLoss of energy

Solution Approach 1:

The system divides processing into specialized functional units (search units, RAKE units, combiner units) that can be independently allocated to different processes. Each unit is designed for specific signal processing tasks, eliminating the need for general-purpose DSPs to handle all operations, thus reducing energy consumption while maintaining flexibility through dynamic allocation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The processor architecture implements dynamic process switching where functional units can be reassigned between processes based on current needs. The system transitions between processes by switching control signals and data routing, avoiding the high overhead of traditional DSP context switching while maintaining adaptability to different communication protocols and processes.

Inventive Principle:

Principle #15Dynamics

2Adaptability or versatility

If general-purpose digital signal processors (DSPs) are used for process switching, then multi-process support is improved, but inter-process overhead increases

Engineering Contradiction:

Improvemulti-process supportVSAvoidinter-process overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The system introduces a central controller as an intermediary that manages process switching and coordinates data flow between functional units. This mediator handles process context management and resource allocation, simplifying the switching mechanism and reducing inter-process overhead compared to complex DSP interrupt handling and context switching.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

Multiple functional units are merged into a unified processor architecture that shares common control logic, data buses, and memory resources. This consolidation reduces the overhead associated with managing separate DSP instances while maintaining the ability to support multiple processes through time-multiplexed resource allocation.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If more digital signal processors (DSPs) are deployed to increase processing power, then computational capacity is improved, but system overhead increases non-linearly

Engineering Contradiction:

Improveprocessing powerVSAvoidsystem overhead

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Each functional unit is designed to perform multiple functions within its domain (e.g., search units can handle different correlation operations, RAKE units can process multiple paths). This multi-functionality allows a smaller number of processors to provide greater total processing power compared to dedicated single-function processors, reducing system overhead while increasing computational capacity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7606576B2Distributed micro instruction set processor architecture for high-efficiency signal processing

Publication Date: 2009.10.20 INTEL CORP

AI summary

A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.