Distributed BIST Circuit Sharing DACs to Cut Chip Area
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Solution Overview
Problem
Existing built-in self-test (BIST) architectures in automotive and other applications require substantial space for dedicated digital-to-analog converters (DACs) due to the need for multiple DACs per monitoring circuit, which is inefficient given that these components are only occasionally used for BISTs.
Innovation Solution
A distributed BIST architecture where components, such as DACs, are shared across adjacent circuits to perform self-tests, allowing one DAC from an adjacent monitoring circuit to provide signals to a comparator in another circuit, thereby reducing the number of DACs needed and saving space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple dedicated DACs are provided per monitoring circuit for BIST, then testing reliability is improved, but chip area increases
Solution Approach 1:
The patent implements a distributed BIST architecture where a single DAC can serve multiple monitoring circuits by selectively coupling its output to different comparators through control logic. This multi-functional approach allows one DAC to generate test signals for several circuits sequentially, eliminating the need for dedicated DACs in each monitoring circuit while maintaining comprehensive testing coverage and reliability
Solution Approach 2:
The patent merges the BIST functionality across multiple monitoring circuits by sharing common test signal generation resources. The control logic coordinates the sharing of DAC outputs among multiple comparators, combining what would traditionally be separate dedicated resources into a unified shared system that achieves the same reliability goals with reduced component count and chip area
2Adaptability or versatility
If multiple dedicated DACs are provided per monitoring circuit for BIST, then testing capability is improved, but device complexity increases
Solution Approach 1:
The control logic implements universal test signal distribution by selectively coupling the shared DAC output to any required comparator based on which circuit needs testing. This single resource performs the work of multiple dedicated DACs, providing equivalent or superior testing capability across all monitoring circuits while reducing the overall number of components and simplifying the device architecture
Solution Approach 2:
The control logic acts as an intermediary that manages the sharing of DAC resources among multiple monitoring circuits. It coordinates the timing and routing of test signals, enabling one DAC to serve multiple functions without requiring complex dedicated connections for each circuit. This intermediary management simplifies the overall system compared to providing direct dedicated DAC connections to every comparator
Data Source
AI summary
Aspects of the present disclosure provide techniques and apparatus for distributed built-in self-test. An example method of testing circuitry includes testing, in a first occasion, a first electrical circuit, having a first component, using at least a second component of a second electrical circuit; and testing, in a second occasion, the second electrical circuit using at least the first component of the first electrical circuit.