Distributed BIST Power Control for SoC Memory Blocks
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Solution Overview
Problem
Modern System on a Chip (SoC) devices face challenges in reducing test power and size during Built-In Self-Test (BIST) testing, which increases power consumption and silicon area due to the need for additional logic gates and test circuitry.
Innovation Solution
The proposed solution involves a distributed BIST architecture with independent power control and isolation circuits for each processor core, coupled with a common BISR controller. This architecture allows for selective power gating, clock gating, and isolation of non-selected memory blocks, enabling fine-grained and coarse-grained tuning of test conditions during BIST testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional logic gates and test circuitry are used for BIST testing, then testing capability is improved, but power consumption increases
Solution Approach 1:
The patent divides the memory system into multiple independently controllable memory blocks, each with its own power gate and clock gate. This segmentation allows the test controller to activate only the specific memory blocks being tested while keeping others in low-power states, thereby reducing overall power consumption during BIST operations while maintaining full testing capability across all memory blocks.
Solution Approach 2:
The patent implements dynamic power management by using power gates and clock gates that can be selectively enabled or disabled based on which memory blocks are currently being tested. The test controller dynamically adjusts the power and clock signals to match the active test requirements, ensuring that power consumption varies dynamically with test activity rather than remaining constantly high.
2Reliability
If additional logic gates and test circuitry are used for BIST testing, then testing capability is improved, but silicon area increases
Solution Approach 1:
The patent designs the power gates and clock gates to serve dual purposes: they function as power management elements during normal operation and as test control elements during BIST operations. The test controller itself is a multi-functional unit that can initialize memory blocks, apply test patterns, and control power/clock gating. This universality reduces the need for separate dedicated test circuitry, thereby minimizing silicon area while maintaining comprehensive testing capability.
Solution Approach 2:
The patent merges the test control functionality with the existing power management infrastructure. The power gates and clock gates are integrated into the memory block architecture itself rather than being added as separate external test equipment. The test controller combines initialization, pattern generation, and power/clock control functions into a single unified unit, reducing overall circuitry and silicon area.
3Productivity
If all memory blocks are tested simultaneously, then testing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic testing by dividing the test sequence into multiple time periods, where different sets of memory blocks are tested in successive periods. The test controller activates power gates and clock gates for one set of memory blocks during a test period, then switches to the next set in the following period. This periodic approach maintains high testing productivity over time while ensuring that at any given moment, only a subset of memory blocks consumes full test power.
Data Source
AI summary
An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.