Distributed Global Bit Line Keeper Circuit for Low Voltage Memory
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Solution Overview
Problem
Existing memory bank systems face challenges with global bit line keeper and precharge devices, which struggle with PVT variations, current leakage, and contention issues, limiting minimum voltage and maximum operating frequency due to large centralized devices and high resistance-capacitance networks.
Innovation Solution
A distributed global bit line keeper/precharge/header circuit is implemented, where each memory bank includes a local keeper-precharge circuit and control circuit, allowing for distributed functionality across multiple banks to manage the global bit line, reducing contention and precharge time, and minimizing power supply stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a centralized precharge device is used at the far end of the global bit line, then the global bit line can be precharged, but the precharge time becomes high which limits the maximum operating frequency
Solution Approach 1:
The centralized precharge device is divided into multiple distributed precharge devices, each located at different memory banks along the global bit line. This segmentation reduces the distance each precharge device must charge, thereby reducing the overall precharge time and enabling higher operating frequencies.
2Reliability
If a large precharge device is used to supply sufficient charge to the global bit line, then the global bit line can be fully precharged, but large current flows through the precharge portion putting stress on the power supply grid
Solution Approach 1:
The large centralized precharge device is segmented into multiple smaller distributed precharge devices located at different memory banks. Each device supplies charge to a local portion of the global bit line, distributing the current load and reducing stress on the power supply grid while maintaining adequate precharge capability.
3Reliability
If a keeper device is used to retain the global bit line state, then the global bit line state is maintained, but contention exists between the keeper device and bit line pull down device which limits the minimum voltage
Solution Approach 1:
The single keeper device is divided into multiple distributed keeper devices, each associated with specific memory banks. This segmentation reduces contention between keepers and pull-down devices by localizing their interaction to smaller subsets of banks, thereby lowering the minimum operating voltage requirement while maintaining state retention reliability.
Data Source
AI summary
According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit.