Distributed Bootstrap Switch Circuit for High-Speed ADC Sampling
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Solution Overview
Problem
Existing bootstrapping techniques for high-speed pipeline analog-to-digital converters face challenges in achieving efficient and accurate signal sampling due to signal-dependent parasitic capacitance and delays, particularly at clock rates exceeding 300 MHz, leading to distortion and reduced sampling precision.
Innovation Solution
A distributed bootstrapping approach with dedicated bootstrapping circuits for each switch, utilizing a capacitor and a thick oxide switch to maintain a constant gate-source voltage independent of the input signal, minimizing parasitic capacitance and optimizing switch design for faster switching and reduced current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single bootstrapping circuit is used to drive multiple switches, then device complexity is reduced, but signal-dependent parasitic capacitance and delays increase, leading to distortion at high clock rates
Solution Approach 1:
The patent divides a single bootstrapping circuit into multiple distributed bootstrapping circuits, with each switch having its own dedicated bootstrapping circuit. This segmentation eliminates signal-dependent parasitic capacitance and delays by isolating each switch's bootstrapping path, thereby improving sampling accuracy at high clock rates while accepting increased device complexity
Solution Approach 2:
The patent applies local quality by making each bootstrapping circuit switch-specific, where each switch has customized bootstrapping capacitance values (C1a, C2a for switch 101a; C1b, C2b for switch 101b) optimized for its local characteristics. This localized optimization minimizes parasitic effects for each individual switch path, improving overall sampling precision
2Measurement precision
If sampling time is increased to eliminate transient effects, then sampling accuracy improves, but productivity decreases due to longer sampling cycles
Solution Approach 1:
The patent uses bootstrapping circuits to pre-charge the gates of switches 101a and 101b to a predetermined voltage level before sampling begins. This preliminary action eliminates transient effects and ensures the switches are fully charged and ready for immediate sampling, allowing maximum sampling time without extending the overall sampling cycle, thus maintaining both accuracy and productivity
Solution Approach 2:
The patent employs periodic clock signals (phase 1, phase 2) to control the bootstrapping circuits and switches in synchronized cycles. This periodic action ensures that sampling occurs at optimal moments when switches are fully charged and parasitic effects are minimized, achieving high sampling accuracy without requiring extended sampling times that would reduce conversion speed
3Reliability
If thick oxide switches are used to handle large voltages, then reliability improves, but device area increases due to larger physical dimensions
Solution Approach 1:
The patent changes the voltage parameter strategy by using bootstrapping circuits to dynamically control the gate-source voltage of thick oxide switches 101a and 101b. Instead of relying solely on large voltage margins, the bootstrapping circuits maintain precise voltage levels (VDD + Vin for switch 101a; VDD + Vflash for switch 101b), allowing the use of smaller thick oxide switches that can handle the controlled voltage levels, thereby reducing device area while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables signal-independent loading, matched sampling, and maximum sampling time, resulting in improved accuracy and reduced distortion, even at high clock rates, by minimizing parasitic capacitance and dynamic current consumption.
Implementation Method 1
A distributed bootstrapping approach with dedicated bootstrapping circuits for each switch, utilizing a capacitor and a thick oxide switch to maintain a constant gate-source voltage independent of the input signal
Data Source
Figure 1A~1B
Figure 2A~2B
Figure 3
AI summary
An input circuit for an analog-to-digital converter (ADC) includes at least one bootstrap circuit, including at least one first switch (SW1:308) for connecting electrical power (VDD) to a first terminal of at least one capacitor (C:304); at least one second switch (SW2:310) for connecting a second terminal of the at least one capacitor to a signal (VIN) to be sampled; at least one third switch (SW3:312) for connecting the first terminal of the at least one capacitor to the control gate (309) of at least one sampling network input switch (306); at least one fourth switch (SW4:314) for connecting the at least one sampling network input switch (306) to a substrate; and at least one fifth switch (SW5:316) for connecting the second terminal of the at least one capacitor to the substrate.