Distributed Buffer Memory Address Sequencer Bandwidth Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face performance bottlenecks due to bandwidth limitations on communication links between the Host, memory control circuits, data buffer circuits, and memory devices, which impact the efficiency of data access and storage operations.
Innovation Solution
A memory system architecture that includes a memory control circuit and data buffer circuits with separate local address sequencers, where the memory control circuit processes commands into write-to-buffer and store-from-buffer operations without sending store data tags to the data buffer circuits, allowing them to manage data storage and retrieval efficiently without explicit location tags, thereby optimizing bandwidth usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If explicit store data tags are sent from memory control circuit to data buffer circuit, then data location accuracy is improved, but communication link bandwidth is consumed
Solution Approach 1:
The patent creates a copy of the address sequencer in both the memory control circuit and data buffer circuit. Each circuit maintains its own local address sequencer that generates address tags independently, eliminating the need to transmit address tags between circuits. This copying approach preserves data location accuracy while eliminating bandwidth consumption for tag transmission.
Solution Approach 2:
The data buffer circuit is equipped with its own address sequencer that autonomously generates address tags without requiring explicit tags from the memory control circuit. This self-service mechanism allows the data buffer circuit to independently determine data locations, eliminating the need for control information transmission while maintaining accurate data placement.
2Manufacturing precision
If memory control circuit manages all address tagging, then data storage precision is improved, but control communication load is increased
Solution Approach 1:
The address tagging function is segmented between two independent address sequencers - one in the memory control circuit and one in the data buffer circuit. This segmentation distributes the control load, with each sequencer handling address generation independently, thereby reducing communication load while maintaining storage precision through coordinated operation.
Solution Approach 2:
The address sequencers are pre-synchronized to generate address tags in advance and in coordination. This preliminary synchronization ensures that both circuits have the necessary address information ready before data transfer, eliminating the need for real-time control communication during critical data operations.
3Stability of the object's composition
If address sequencers are synchronized across distributed circuits, then data access coordination is improved, but synchronization overhead is increased
Solution Approach 1:
The address sequencers operate continuously and autonomously once synchronized, generating address tags without requiring continuous synchronization signals. This continuous autonomous operation maintains data access coordination while minimizing synchronization overhead to periodic or initial synchronization events only.
Data Source
AI summary
One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communications links in a memory system. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. In one embodiment, the Host only transmits data over its communications link with the data buffer circuit. In one aspect, the memory control circuit does not send a control signal to the data buffer circuits. In one aspect, the memory control circuit and the data buffer circuits each maintain a separate state machine-driven address pointer or local address sequencer, which contains the same tags in the same sequence. In another aspect, a resynchronization method is disclosed.