Distributed Bus Arbiter for One-Cycle Channel Selection
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Solution Overview
Problem
In disaggregated memory systems, memory bus transactions from multiple master components to shared remote slaves over serial channels face challenges in maintaining inter-channel ordering constraints, leading to potential serialization issues and performance degradation due to concurrent requests and arbitrary interleaving of data.
Innovation Solution
A distributed bus arbiter is implemented for one-cycle channel selection, using bit-masks and a FIFO queue to ensure correct serialization of memory bus transactions by filtering input masks and enforcing channel constraints, allowing for serialization of transactions across multiple masters and slaves in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bus transactions from multiple master components are allowed to access shared remote slaves concurrently over serial channels, then system throughput and productivity are improved, but inter-channel ordering constraints cannot be maintained, leading to data integrity issues and serialization errors
Solution Approach 1:
A distributed bus arbiter is introduced as an intermediary component between multiple master bus components and shared remote slaves. The arbiter receives transactions from multiple masters, serializes them according to inter-channel ordering constraints, and forwards them to the appropriate slaves over serial channels. This mediator ensures that concurrent access does not violate ordering requirements, thereby maintaining data integrity while allowing high throughput.
Solution Approach 2:
The distributed bus arbiter performs preliminary serialization and ordering of memory bus transactions before they are transmitted over serial channels. By pre-ordering transactions based on inter-channel ordering constraints and selecting channels in advance, the system ensures that ordering is maintained without requiring complex coordination during transaction execution, thus preserving data integrity while enabling concurrent processing.
2Reliability
If strict inter-channel ordering constraints are enforced for all memory bus transactions, then data integrity and reliability are maintained, but transaction processing time increases and productivity decreases
Solution Approach 1:
The distributed bus arbiter performs preliminary ordering and channel selection for transactions that require inter-channel ordering constraints. By determining the correct sequence and channel assignment in advance, transactions can be processed efficiently without repeated serialization delays. This preliminary action ensures data integrity while minimizing the impact on processing speed.
Solution Approach 2:
The system dynamically adjusts the level of ordering enforcement based on transaction characteristics. The distributed bus arbiter identifies transactions that require inter-channel ordering constraints and applies serialization only to those specific cases, while allowing concurrent processing for transactions that do not require ordering. This dynamic approach maintains data integrity for constrained transactions while maximizing overall system throughput.
3Reliability
If a traditional centralized bus arbiter is used to manage memory bus transactions, then inter-channel ordering can be maintained, but the system becomes a bottleneck and productivity is limited
Solution Approach 1:
The centralized bus arbiter functionality is segmented and distributed to multiple components. Instead of a single centralized arbiter, the system employs distributed bus arbiters at different locations in the memory interconnect. Each distributed arbiter independently manages ordering and channel selection for its local transactions, eliminating the single-point bottleneck while maintaining ordering constraints through coordinated operation across the distributed architecture.
4Productivity
If multiple master bus components access shared remote slaves simultaneously over parallel channels, then productivity is improved, but arbitrary interleaving of data occurs and serialization correctness cannot be guaranteed
Solution Approach 1:
Distributed bus arbiters act as intermediaries that receive concurrent transactions from multiple masters, serialize them according to inter-channel ordering constraints, and forward them over serial channels. This mediation ensures that arbitrary interleaving is prevented while maintaining high concurrent access capability, as the arbiters coordinate channel assignment and transaction ordering to guarantee serialization correctness.
Solution Approach 2:
The distributed bus arbiters perform preliminary channel selection and transaction ordering before transactions are transmitted over serial channels. By determining the correct serialization sequence in advance based on inter-channel ordering constraints, the system ensures that concurrent access does not lead to arbitrary interleaving, thereby guaranteeing serialization correctness while maintaining productivity.
Data Source
AI summary
Embodiments using a distributed bus arbiter for one cycle channel selection with inter-channel ordering constraints. A distributed bus arbiter that orders one or more memory bus transactions originating from a plurality of master bus components to a plurality of shared remote slaves over shared serial channels attached to differing interconnect instances may be implemented.