Distributed Cache Slices for Multi-Core Memory Coherency
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Solution Overview
Problem
In multi-core processors, providing each core with a cache system leads to inefficient bandwidth usage due to duplication of data access from external memory, and lack of coherent memory view between cores, resulting in processing errors and performance reduction.
Innovation Solution
Implementing a distributed cache system with multiple cache slices, each connected to a core and interconnected via crossbars, allowing memory access requests to be forwarded to the appropriate cache slice, thereby reducing data duplication and improving memory coherency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If each core is provided with a cache system, then the processing performance of each core is improved, but the bandwidth efficiency deteriorates due to data duplication
Solution Approach 1:
The patent merges the cache systems of multiple cores into a single shared cache structure. Instead of each core having its own independent cache, all cores access a common cache memory through shared interconnects, eliminating data duplication across cores while maintaining fast access speeds for all processors.
Solution Approach 2:
The shared cache system serves multiple functions simultaneously: it acts as cache memory for all cores, provides a unified memory view across the processor, and enables coherent data access. This multi-functional design eliminates the need for separate cache systems while maintaining performance benefits.
2Productivity
If each core is provided with a cache system, then the processing performance of each core is improved, but the memory coherency deteriorates due to lack of coherent view between cores
Solution Approach 1:
By merging individual core caches into a single shared cache structure, the patent establishes a unified memory view that all cores can access coherently. This eliminates the coherence problems that arise when each core maintains its own independent cache, as all cores now see the same data in the shared cache.
Solution Approach 2:
The shared cache acts as an intermediary between all cores and the external memory. It mediates data access for all cores, ensuring that data is fetched once and made available to all cores, thereby maintaining memory coherence while improving access performance.
3Speed
If a cache is included within the PU, then the data access speed is improved, but the chip space and manufacturing cost increase
Solution Approach 1:
The patent combines the cache functionality with existing structures in the processor architecture, sharing resources such as interconnects and control logic. This merging approach provides fast data access through caching while minimizing the additional chip space required compared to implementing separate independent caches for each core.
Data Source
AI summary
A processor has first and second cores and a distributed cache that caches a copy of data stored at a plurality of memory addresses of a memory. A first cache slice is connected to the first core, and a second cache slice is connected to the second core. The first cache caches a copy of data stored at a first set of memory addresses, and the second cache slice caches a copy of data stored at a second, different, set of memory addresses.