Distributed Cache Directory with Dual Sub-Network Architecture
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Solution Overview
Problem
Current cache coherence management systems in multiprocessor architectures face inefficiencies due to centralized list representation, which leads to increased network traffic and saturation of memory resources, especially as the number of shared data lines grows, and imposes suboptimal message paths that slow down system performance.
Innovation Solution
Implementing a dual sub-network architecture with distinct message transmission protocols, where one sub-network handles cache coherence management messages requiring read/write access and another handles processing data transmission without such access, optimizing message routing and reducing network congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a centralized list representation is used for cache coherence management, then the system can maintain cache consistency, but network traffic increases and memory resources become saturated
Solution Approach 1:
The patent divides the centralized list representation into distributed segments across multiple cache nodes. Instead of one central directory maintaining all cache line information, each node maintains local directory information, segmenting the coherence management function across the network to reduce traffic on any single path and distribute memory access load.
Solution Approach 2:
The patent transitions from a single-dimension centralized list to a multi-dimensional distributed directory structure. Cache line information is organized across multiple dimensions including node location, cache set, and validity state, allowing coherence management to proceed in parallel across different dimensional layers rather than through a single centralized bottleneck.
2Reliability
If a centralized list representation is used for cache coherence management, then the system can maintain cache consistency, but system performance slows down due to suboptimal message paths
Solution Approach 1:
The patent implements local quality by allowing each cache node to make coherence decisions based on local directory information rather than requiring all coherence operations to traverse through a central controller. Each node has the authority and information needed to handle local coherence events, improving performance by eliminating unnecessary message routing through suboptimal paths.
Solution Approach 2:
The patent applies preliminary action by pre-computing and storing directory information locally at each cache node before coherence conflicts arise. Validity bits, cache line information, and mapping data are maintained in advance at appropriate locations, so when coherence events occur, decisions can be made immediately using pre-positioned information rather than querying through the network.
3Adaptability or versatility
If the number of shared data lines increases, then the system can support more processors and data, but network traffic and memory saturation increase
Solution Approach 1:
The patent segments the directory information for multiple shared data lines across different cache nodes based on data line address ranges or cache sets. As the number of shared data lines increases, the segmented distribution automatically scales, with each node managing a portion of the total data lines, preventing network traffic and memory access from concentrating on a single resource.
Solution Approach 2:
The patent adds dimensional organization to handle increased numbers of shared data lines by introducing address space partitioning and cache set dimensions. Data lines are mapped to nodes not just by proximity but by address range and set membership, creating a multi-dimensional allocation scheme that scales efficiently as more data lines and processors are added to the system.
Data Source
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Figure 3
AI summary
This system for processing data with management of a consistency of caches in a network (14, 16) of processors (??1, ??2,..., ??16) furnished with cache memories (L2, L1, L12, L116), said network comprising a plurality of interconnected nodes (16A, 16B, 16C, 16D, 16E, 16F) for accessing a main memory, comprises a set of directories (18A, 18B, 18C, 18D, 18E, 18F) distributed among the nodes of the network, each directory comprising a look-up table of correspondence between rows of caches and fields of information on these rows of caches. It comprises a first sub-network (R1) for interconnection of the nodes, implementing a first message transmission protocol providing for read/write access to the directories during any passage via the corresponding nodes of a message travelling through this first sub-network, and a second sub-network (R2) for interconnection of the nodes, implementing a second message transmission protocol excluding any read/write access to the directories during any passage via the corresponding nodes of a message travelling through this second sub-network.