Distributed Channels for Spatial Processing Memory Allocation

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Solution Overview

Problem

In computing systems with spatial processing units (SPUs), the inefficiencies arise from the allocation of memory ports and completion buffers due to varying algorithm requirements, leading to wasted resources and potential deadlocks during memory operations.

Innovation Solution

Implementing distributed memory operations using distributed channels that associate multiple processing elements with shared memory controllers, and maintaining a shared completion buffer and ordering buffer to optimize memory access and request handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If memory ports are allocated to each processing element, then memory access capability is improved, but resource wastage increases when not all processing elements communicate with memory simultaneously

Engineering Contradiction:

Improvememory access capabilityVSAvoidresource wastage

Core Design Contradiction:

SpeedVSLoss of energy

Solution Approach 1:

The patent implements a shared memory port that can be dynamically allocated to different processing elements based on algorithm requirements. Instead of dedicating memory ports to individual processing elements, the system uses a universal memory port that serves multiple processing elements, reducing resource wastage while maintaining memory access capability when needed.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs dynamic allocation of memory ports and completion buffers based on runtime conditions. The system adjusts the number of memory ports and buffer sizes according to the specific algorithm being executed and the current communication patterns, allowing the system to optimize between speed and resource usage dynamically rather than being fixed.

Inventive Principle:

Principle #15Dynamics

2Reliability

If completion buffers are allocated to each processing element, then memory operation completion tracking is improved, but resource wastage and potential deadlocks increase

Engineering Contradiction:

Improvememory operation completion trackingVSAvoidresource wastage

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent merges individual completion buffers into a shared completion buffer that serves multiple processing elements. This consolidation reduces the total buffer memory required while maintaining the ability to track completion status of memory operations. The shared buffer eliminates redundant buffer allocations and reduces the risk of deadlocks associated with individual buffer management.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared completion buffer acts as a universal resource that can track completion status for memory operations initiated by any processing element. This multi-functional buffer replaces multiple dedicated buffers, reducing overall resource consumption while maintaining reliable tracking of memory operation completions across the system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Productivity

If distributed channels are implemented to share memory controllers, then resource utilization is improved, but system complexity increases

Engineering Contradiction:

Improveresource utilizationVSAvoidsystem complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces distributed channels as intermediary components between processing elements and the shared memory controller. These channels manage the complexity of shared resource access by providing structured communication paths and coordination mechanisms, allowing multiple processing elements to efficiently share memory controllers without direct complex interactions between them.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Loss of energy

If memory ports are dynamically allocated based on algorithm requirements, then resource wastage is reduced, but allocation overhead increases

Engineering Contradiction:

Improveresource wastageVSAvoidallocation overhead

Core Design Contradiction:

Loss of energyVSLoss of time

Solution Approach 1:

The patent performs preliminary allocation of memory ports and completion buffers based on static analysis of algorithm characteristics before execution. By determining the memory access patterns and communication requirements in advance, the system can pre-configure appropriate resource allocation, reducing both waste and runtime allocation overhead during actual execution.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10331583B2Executing distributed memory operations using processing elements connected by distributed channels

Publication Date: 2019.06.25 INTEL CORP

AI summary

A processing device for executing distributed memory operations using spatial processing units (SPU) connected by distributed channels is disclosed. A distributed channel may or may not be associated with memory operations, such as load operations or store operations. Distributed channel information is obtained for an algorithm to be executed by a group of spatially distributed processing elements. The group of spatially distributed processing elements can be connected to a shared memory controller. For each distributed channel in the distributed channel information, one or more of the group of spatially distributed processing elements may be associated with the distributed channel based on the algorithm. By associating the spatially distributed processing elements to a distributed channel, the functionality of the processing element can vary depending on the algorithm mapped onto the SPU.