Distributed Chip-Stack Semiconductor Package for Low Profile
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving reduced thickness while maintaining high performance and capacitance, particularly in embedding multiple semiconductor chips and a control chip effectively.
Innovation Solution
A semiconductor package design featuring a substrate with interconnection circuits, a controller chip, buffer chip, and multiple chip stacks, where the first and second chip stacks are directly connected to the controller chip, and the third chip stack is connected through a buffer chip, allowing for a distributed configuration that reduces height without compromising electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are embedded together in a single package, then high performance and high capacitance are achieved, but the package thickness increases
Solution Approach 1:
The patent transitions from vertical stacking to horizontal distribution by placing multiple chip stacks (first, second, and third chip stacks) side-by-side on the substrate. This dimensional change allows multiple chips to be accommodated in the plane rather than stacking them vertically, thereby reducing package thickness while maintaining high chip density and capacitance.
Solution Approach 2:
The patent divides the semiconductor chips into multiple separate stacks (first chip stack, second chip stack, third chip stack) that are spatially distributed across the substrate. Each stack is independently connected to the controller chip through the interconnection circuit, enabling parallel organization that reduces vertical height while preserving functional capacity.
2Length of moving object
If chip stacks are distributed across the substrate, then package thickness is reduced, but electrical connection complexity increases
Solution Approach 1:
The controller chip serves multiple functions by establishing electrical connections with all three chip stacks through the interconnection circuit. This multi-functional design simplifies the overall system architecture by using a single control unit to manage multiple distributed stacks, reducing connection complexity despite spatial distribution.
Solution Approach 2:
The interconnection circuit acts as an intermediary between the controller chip and the distributed chip stacks. This mediator layer manages the electrical connections systematically, providing a standardized interface that simplifies the complexity of connecting multiple stacks to the controller while maintaining signal integrity.
3Reliability
If all chip stacks are directly connected to the controller chip, then signal integrity is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent applies different connection configurations to different chip stacks based on their functional requirements. The first and second chip stacks are directly connected to the controller chip for optimal signal integrity, while the third chip stack is connected through the buffer chip to simplify manufacturing. This localized differentiation maintains high signal quality where needed while easing manufacturing constraints.
Solution Approach 2:
The buffer chip serves as an intermediary for the third chip stack, providing a simplified connection path that reduces manufacturing complexity. This mediator allows the third stack to be integrated more easily into the package while still maintaining acceptable electrical characteristics through the buffer interface.
Data Source
AI summary
A semiconductor package includes a substrate, a controller chip on a first surface of the substrate, a first chip stack on the controller chip, a second chip stack on the substrate in adjacent spaced apart relationship with the first chip stack, a third chip stack including a first group of semiconductor chips above or below the first chip stack and a second group of semiconductor chips above or below the second chip stack. A buffer chip is on the substrate between the first chip stack and the second chip stack, and the buffer chip is electrically connected to the third chip stack and the controller chip. An encapsulant encapsulates at least a portion of the first chip stack, the second chip stack, and the third chip stack. Connection bumps are on an opposite second surface of the substrate. The first chip stack and the second chip stack are directly electrically connected to the controller chip, and the third chip stack is electrically connected to the controller chip by the buffer chip.