Distributed Circuit Design Compilation with Synchronization Protocol
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Solution Overview
Problem
The compilation of large complex electronic circuit designs into gate-level netlists is bottlenecked by the slow execution speed of software-based simulation, leading to significant delays in the verification process, especially for System-on-Chip designs.
Innovation Solution
A distributed computing system employing multiple participating processes that compile different portions of a circuit design in parallel, utilizing a synchronization protocol to manage operational states and transition phases, allowing for synchronous compilation and deployment in an emulator for verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a monolithic software application is used to compile the gate-level netlist, then the compilation can be completed given enough time and processing resources, but the compilation delay becomes a bottleneck in the verification process
Solution Approach 1:
The patent divides the compilation process into multiple phases (e.g., front-end, middle-end, back-end) and further segments the netlist into different portions that can be compiled in parallel by multiple participating processes. This segmentation enables concurrent compilation of different circuit design portions, significantly reducing overall compilation time while maintaining reliability through coordinated phase transitions managed by a synchronization protocol.
2Reliability
If software-based simulation is used for functional verification, then the logical design can be verified, but the execution speed drops significantly as design size increases
Solution Approach 1:
The patent replaces software-based simulation with hardware-based emulation. The compiled gate-level netlist is deployed to an emulator that uses reconfigurable hardware (such as FPGAs or ASIC-based emulators) to physically implement and verify the circuit design. This substitution leverages parallel hardware architecture to achieve verification speeds that are orders of magnitude faster than software simulation, especially for large System-on-Chip designs.
Data Source
AI summary
This application discloses a distributed computing system implementing multiple participating processes to separately compile different portions of a circuit design describing an electronic device over multiple phases. The distributed computing system can implement a management process to utilize a synchronization protocol to identify operational states of the participating processes during compilation of the different portions of the circuit design, maintain the operational states of the participating processes, and separately determine when the participating processes have completed compilation of the circuit design portions for one of the phases based on the operational states of the participating processes. The management process can determine to have the participating processes synchronously transition to another one of the phases or that the participating processes have compiled the circuit design into a compiled design corresponding to the circuit design, and deploy the compiled design in an emulator for verification of a functionality of the electronic device.