Distributed Circuit Test Algorithm Queuing for Parallel Processing
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Solution Overview
Problem
Current automated circuit testing algorithms face challenges in achieving high fault coverage while minimizing test costs and chip area overhead, particularly due to the increasing complexity and data volume of integrated circuits, which leads to inefficiencies in test pattern generation and fault simulation.
Innovation Solution
The method involves distributing the execution of circuit testing algorithms across a network of processors, where task allocation is managed based on queue lengths and processor availability, allowing for parallel processing and efficient resource utilization, and isolating random number generation to ensure consistent results across distributed and non-distributed executions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If automated test pattern generation algorithms are used to achieve high fault coverage, then the quality of circuit testing is improved, but the computational time and cost increase significantly
Solution Approach 1:
The patent divides the circuit into multiple partitions and distributes test pattern generation tasks across multiple processors. Each processor handles a specific partition or subset of faults, allowing parallel computation. This segmentation enables the system to achieve high fault coverage through comprehensive testing while reducing the computational time by performing multiple test generations simultaneously rather than sequentially.
2Measurement precision
If deterministic test pattern generation is performed to target specific faults, then the precision of fault detection is improved, but the complexity of the testing algorithm increases
Solution Approach 1:
The patent segments the fault detection process into deterministic and random components. Deterministic test patterns target specific critical faults with high precision, while random pattern generation handles remaining faults. This segmentation allows the system to maintain high fault detection precision for critical issues without requiring complex deterministic algorithms for all faults, thereby reducing overall algorithm complexity.
Solution Approach 2:
The patent applies partial deterministic action by using deterministic test generation only for critical or high-priority faults, while using random pattern generation for the remaining faults. This partial application of deterministic methods maintains sufficient fault detection precision for critical issues while avoiding the excessive complexity that would result from applying deterministic algorithms to all faults.
3Productivity
If multiple processors are used to parallelize test pattern generation, then the productivity of the testing process is improved, but the coordination overhead and communication requirements increase
Solution Approach 1:
The patent segments the fault list and circuit partitions among multiple processors, with each processor independently handling its assigned tasks. This segmentation minimizes coordination overhead by reducing the need for frequent communication between processors. Each processor can generate test patterns for its assigned partition autonomously, improving productivity while keeping system coordination complexity manageable.
Solution Approach 2:
The patent introduces a master processor or coordination mechanism that manages task distribution and result aggregation among worker processors. This intermediary handles the coordination overhead by centralizing the management of task allocation and result collection, allowing worker processors to focus on test pattern generation without complex peer-to-peer coordination, thus improving overall productivity while managing system complexity.
4Ease of operation
If random pattern generation is used to fill unspecified test values, then the ease of operation is improved, but the fault coverage may be insufficient compared to deterministic methods
Solution Approach 1:
The patent merges deterministic and random test pattern generation methods into a hybrid approach. Deterministic methods are used to generate test patterns for critical faults with high fault coverage, while random pattern generation fills unspecified values and handles remaining faults. This combination maintains the ease of operation of random generation while achieving the high fault coverage of deterministic methods, resolving the contradiction between simplicity and effectiveness.
Data Source
AI summary
Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and fault simulation algorithms. Those algorithms that are independent from each other can be executed non-sequentially (e.g., in parallel). Allocation of the various algorithm portions for execution among various processors can be based in part on a queue length associated with the processor. The queue length is adjustable based on many factors including data indicating the status of an execution maintained by the controlled processors. The faster processors can have their queue lengths increased. Multiple queue lengths can be maintained to allow for changes in allocation based on the granularity of tasks being performed by the controlling processor.