Distributed Clock Generation for Functional Block Synchronization
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Solution Overview
Problem
As integrated circuits increase in scale and complexity, clock delay times and skew issues become more significant, making timing design for data synchronization between circuit blocks more difficult, especially with increasing clock frequencies and longer interconnect distances on chip top layers.
Innovation Solution
The implementation of a clock supply system with multiple generation units, each equipped with a counter and frequency division circuit, which frequency-divides a reference clock to supply clocks to functional blocks, allowing for reduced clock delay differences and improved timing convergence by shortening clock routing and using common clock lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single clock generator is used to supply clocks to all functional blocks, then the device complexity is reduced, but the clock delay difference increases due to long interconnect distances
Solution Approach 1:
The patent divides the single clock generator into multiple distributed generation units (6a-6f), each supplying clocks to nearby functional blocks. This segmentation reduces clock routing distances and minimizes delay differences while maintaining manageable system complexity through modular design.
2Adaptability or versatility
If the circuit scale is increased to improve functionality, then the processing capability is enhanced, but the clock delay time increases due to longer distances from clock source
Solution Approach 1:
By distributing multiple clock generation units throughout the circuit, the patent enables the circuit scale to expand while keeping clock delay times short. Each functional block receives clocks from nearby generation units, preventing clock delay increase even as the overall circuit grows.
Solution Approach 2:
The patent transitions from a single centralized clock source to a distributed network of clock generation units arranged across the chip. This spatial redistribution allows the system to accommodate larger circuit scales without proportionally increasing clock delay times.
3Productivity
If the clock frequency is increased to improve processing speed, then the productivity is enhanced, but the timing design difficulty increases due to reduced timing margins
Solution Approach 1:
The distributed clock generation units enable higher clock frequencies by ensuring short clock paths to each functional block. This segmentation maintains timing margins even at high frequencies, reducing timing design complexity despite the increased processing speed.
4Ease of operation
If multiple generation units are used to reduce clock delay differences, then the timing design is simplified, but the device complexity increases
Solution Approach 1:
The patent uses segmentation to create multiple clock generation units that simplify timing design by reducing delay variations. While this increases the number of components, the modular nature of the segmentation keeps the overall system complexity manageable and the timing design benefits significant.
Data Source
AI summary
There is provided with an information processing apparatus. A plurality of functional blocks are in synchronization relationship. Each of a plurality of generation units comprises a counter and a frequency division circuit. The frequency division circuit frequency-divides a reference clock based on a value of the counter. Each of the plurality of generation units supplies a clock generated using the reference clock to a corresponding functional block among the plurality of functional blocks.