Distributed Clock Synchronization for Closed-Loop Control Testing

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Solution Overview

Problem

Existing checking apparatuses for testing closed-loop control units face challenges in synchronizing computation units over long distances, leading to inaccuracies in temporal association and potential time drift issues, which are exacerbated by the limitations of previous networking and synchronization solutions.

Innovation Solution

A checking apparatus that includes a first computation unit for executing a model code, a time signal converter unit, and a timing transmission unit to generate periodic timing signals, allowing for synchronization of computation units over distances of several hundred meters or kilometers, using a global time signal source and a multiplexer to stabilize and switch between frequency-stabilized timing signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of stationary object

If computation units are synchronized using conventional networking solutions over long distances, then the checking apparatus can test closed-loop control units with distributed computation units, but time drift and inaccuracies in temporal association occur

Engineering Contradiction:
Improvedistance between computation unitsVSAvoidtemporal association accuracy
Core Design Contradiction:
Length of stationary objectVSMeasurement precision

Solution Approach 1:

A dedicated timing signal transmission path acts as an intermediary between the timing signal source and computation units. This separate synchronization channel independent of data communication pathways provides precise timing references even over long distances, eliminating time drift issues that plague conventional networking solutions.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent replaces conventional electronic networking synchronization mechanisms with optical timing signal transmission. Optical timing signals provide superior temporal precision and stability compared to electrical signal-based networking protocols, enabling accurate synchronization across vast distances without the time drift inherent in electrical communication systems.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Device complexity

If conventional timing synchronization methods are used, then the apparatus structure remains simple, but clock signal changes and time drift issues arise

Engineering Contradiction:
Improvesynchronization system structureVSAvoidtiming synchronization stability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The synchronization system is segmented into dedicated components: a timing signal source, separate timing signal transmission paths, and timing signal receivers at each computation unit. This segmentation isolates the critical timing function from data communication and control functions, preventing interference and ensuring reliable timing synchronization even as system complexity increases.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The timing signal transmission infrastructure serves multiple functions simultaneously: providing synchronization references to all computation units, establishing temporal associations for distributed testing, and enabling coordinated operation across the entire checking apparatus. This multi-functionality justifies the added structural complexity by delivering comprehensive timing solutions.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11169208B2Inspection device
Publication Date: 2021.11.09 DSPACE DIGITAL SIGNAL PROCESSING & CONTROL ENGINEERING GMBH
  • US11169208B2 patent drawing

AI summary

A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.