Distributed Clock Divider Layout for Low-OCV Timing
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Solution Overview
Problem
In VLSI hardware modules, multiple clock domains with synchronous clocks can cause on-chip variations (OCV) due to clock skew, making clock balancing and static-timing analysis challenging, especially when clock dividers are centrally located near the phase-locked loop (PLL).
Innovation Solution
Placing clock dividers at remote locations on the chip, allowing for programmable frequency division of the PLL clock to generate sub-multiple clocks, with synchronization controlled by external signals, enabling precise clock edge control for different modes, including design-for-test (DFT).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If clock dividers are placed at a central location near the PLL, then clock distribution is simplified, but on-chip variation and clock skew increase
Solution Approach 1:
The patent divides the centralized clock divider into multiple distributed clock dividers placed at different locations on the chip. Each clock divider is assigned to a specific clock domain, segmenting the clock distribution system to reduce on-chip variations while maintaining manageable complexity through localized clock generation.
Solution Approach 2:
The patent implements local clock division by placing clock dividers adjacent to their respective clock domains rather than centrally. This local quality approach allows each domain to have its own clock division capability, improving timing precision by eliminating long clock distribution paths while keeping the overall system complexity distributed and manageable.
2Productivity
If multiple clock domains operate at different frequencies, then speed and power optimization is improved, but clock balancing and timing analysis become more difficult
Solution Approach 1:
The patent implements programmable clock dividers that can dynamically adjust division ratios to generate different clock frequencies for different domains. This dynamic capability allows the system to optimize for speed and power by selecting appropriate frequencies while the programmable nature simplifies clock balancing through flexible adjustment rather than fixed complex routing.
Solution Approach 2:
The patent changes the division ratio parameter of clock dividers to generate different clock frequencies for different domains. By programmably adjusting this parameter, the system achieves speed and power optimization through frequency selection while simplifying clock balancing through parameter control rather than physical routing complexity.
3Manufacturing precision
If clock dividers are distributed at remote locations, then on-chip variation is reduced, but device complexity increases
Solution Approach 1:
The patent segments the clock distribution system by placing dedicated clock dividers at remote locations adjacent to each clock domain. This segmentation reduces on-chip variations by eliminating long distribution paths while managing complexity through functional decomposition, where each distributed divider is a simple, standardized unit.
Solution Approach 2:
The patent uses identical or standardized clock divider designs distributed to multiple locations on the chip. This copying approach reduces on-chip variations through consistent local clock generation while managing complexity through reuse of proven designs, eliminating the need for complex custom routing for each clock domain.
Data Source
AI summary
This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.