Distributed Clock Tamper Detection in IC Clock Trees
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit clock detection systems are vulnerable to external manipulation, as frequency detection cells are easily locatable and modifiable, do not cover critical points, and lack self-test functions to detect tampering of the monitoring system.
Innovation Solution
A circuit configuration with multiple clock detectors monitoring frequency and duty cycle parameters, placed at critical points within the integrated circuit, concealed as standard cells, generating an alarm signal upon deviation, and connected to a network for integrity verification, including periodic self-test functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single frequency detection cell is used, then the device complexity is low, but the reliability is insufficient because it can be easily located and modified by attackers
Solution Approach 1:
The patent divides the frequency detection function into multiple distributed detection cells placed at different critical points within the clock tree. Each cell independently monitors local clock signals, making the overall system more reliable because an attacker would need to compromise multiple distributed points rather than a single centralized detector.
Solution Approach 2:
The detection cells are nested within standard digital logic structures (such as flip-flops or logic gates) that are already present in the circuit. This allows the security function to be embedded within the existing circuit architecture without adding significant external complexity, as the detectors utilize existing circuit resources.
2Measurement precision
If frequency detection is performed at a single point, then the device complexity is low, but the measurement precision is insufficient to detect manipulation at critical points
Solution Approach 1:
Multiple detection cells are distributed throughout the clock distribution network at critical points where clock signals are used. This segmentation allows precise local monitoring of clock signals at each critical point, enabling detection of manipulations that would be missed by a single global detector.
Solution Approach 2:
The patent transitions from single-point detection to multi-point spatial distribution of detectors. By adding the spatial dimension of multiple detection locations throughout the clock tree, the system achieves comprehensive coverage of critical points while maintaining manageable complexity through modular cell design.
3Reliability
If a global protection mechanism is implemented, then the device complexity is low, but the reliability is insufficient because it does not cover locally critical points
Solution Approach 1:
The protection system is segmented into multiple independent detection cells, each responsible for monitoring a specific local region or critical point in the clock distribution network. This ensures that locally critical points receive dedicated protection while the overall system maintains comprehensive coverage through the distributed architecture.
4Ease of operation
If the clock detector uses standard digital logic structures, then the ease of operation is improved for concealment, but the difficulty of detecting and measuring increases for security verification
Solution Approach 1:
The detection cells are designed with local quality by camouflaging them as standard digital logic structures (such as flip-flops, latches, or logic gates) that blend in with the surrounding circuitry. Each cell's external behavior matches that of standard cells, making them indistinguishable through conventional inspection methods while maintaining their security monitoring function internally.
Data Source
AI summary
A circuit configuration for secure application includes several internal frequency detectors arranged in digital units at critical points of an integrated circuit. The clock detectors are concealed in the digital part of the integrated circuit each as a standard cell (flip-flop unit) in order to prevent any external manipulation and in order to hide its function. The clock detectors are preferably disposed in a clock tree topology, which can be at several levels for distributing the clock signal through the different digital unit tree at critical points. Alarms are generated via a clock detector network if at any level an external clock attack has been monitored.